664 lines
18 KiB
C
664 lines
18 KiB
C
/*
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* Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
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* Copyright (C) 2013 Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clk.h>
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/* Board oscillator frequency */
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#ifndef CONFIG_ZYNQ_PS_CLK_FREQ
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# define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL
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#endif
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/* Register bitfield defines */
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#define PLLCTRL_FBDIV_MASK 0x7f000
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#define PLLCTRL_FBDIV_SHIFT 12
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#define PLLCTRL_BPFORCE_MASK (1 << 4)
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#define PLLCTRL_PWRDWN_MASK 2
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#define PLLCTRL_PWRDWN_SHIFT 1
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#define PLLCTRL_RESET_MASK 1
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#define PLLCTRL_RESET_SHIFT 0
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#define ZYNQ_CLK_MAXDIV 0x3f
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#define CLK_CTRL_DIV1_SHIFT 20
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#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
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#define CLK_CTRL_DIV0_SHIFT 8
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#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
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#define CLK_CTRL_SRCSEL_SHIFT 4
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#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
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#define CLK_CTRL_DIV2X_SHIFT 26
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#define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
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#define CLK_CTRL_DIV3X_SHIFT 20
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#define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
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#define ZYNQ_CLKMUX_SEL_0 0
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#define ZYNQ_CLKMUX_SEL_1 1
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#define ZYNQ_CLKMUX_SEL_2 2
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#define ZYNQ_CLKMUX_SEL_3 3
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DECLARE_GLOBAL_DATA_PTR;
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struct clk;
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/**
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* struct zynq_clk_ops:
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* @set_rate: Function pointer to set_rate() implementation
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* @get_rate: Function pointer to get_rate() implementation
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*/
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struct zynq_clk_ops {
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int (*set_rate)(struct clk *clk, unsigned long rate);
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unsigned long (*get_rate)(struct clk *clk);
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};
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/**
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* struct clk:
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* @name: Clock name
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* @frequency: Currenct frequency
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* @parent: Parent clock
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* @flags: Clock flags
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* @reg: Clock control register
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* @ops: Clock operations
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*/
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struct clk {
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char *name;
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unsigned long frequency;
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enum zynq_clk parent;
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unsigned int flags;
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u32 *reg;
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struct zynq_clk_ops ops;
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};
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#define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1
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static struct clk clks[clk_max];
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/**
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* __zynq_clk_cpu_get_parent() - Decode clock multiplexer
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* @srcsel: Mux select value
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* Returns the clock identifier associated with the selected mux input.
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*/
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static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
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{
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unsigned int ret;
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switch (srcsel) {
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case ZYNQ_CLKMUX_SEL_0:
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case ZYNQ_CLKMUX_SEL_1:
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ret = armpll_clk;
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break;
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case ZYNQ_CLKMUX_SEL_2:
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ret = ddrpll_clk;
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break;
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case ZYNQ_CLKMUX_SEL_3:
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ret = iopll_clk;
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break;
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default:
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ret = armpll_clk;
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break;
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}
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return ret;
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}
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/**
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* ddr2x_get_rate() - Get clock rate of DDR2x clock
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* @clk: Clock handle
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* Returns the current clock rate of @clk.
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*/
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static unsigned long ddr2x_get_rate(struct clk *clk)
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{
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u32 clk_ctrl = readl(clk->reg);
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u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
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return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
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}
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/**
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* ddr3x_get_rate() - Get clock rate of DDR3x clock
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* @clk: Clock handle
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* Returns the current clock rate of @clk.
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*/
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static unsigned long ddr3x_get_rate(struct clk *clk)
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{
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u32 clk_ctrl = readl(clk->reg);
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u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
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return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
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}
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static void init_ddr_clocks(void)
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{
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u32 div0, div1;
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unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
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u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
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/* DDR2x */
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clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
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clks[ddr2x_clk].parent = ddrpll_clk;
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clks[ddr2x_clk].name = "ddr_2x";
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clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
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clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
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/* DDR3x */
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clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
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clks[ddr3x_clk].parent = ddrpll_clk;
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clks[ddr3x_clk].name = "ddr_3x";
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clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
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clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
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/* DCI */
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clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
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div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
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div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
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clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
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clks[dci_clk].parent = ddrpll_clk;
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clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
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DIV_ROUND_CLOSEST(prate, div0), div1);
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clks[dci_clk].name = "dci";
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gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
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}
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static void init_cpu_clocks(void)
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{
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int clk_621;
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u32 reg, div, srcsel;
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enum zynq_clk parent;
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reg = readl(&slcr_base->arm_clk_ctrl);
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clk_621 = readl(&slcr_base->clk_621_true) & 1;
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div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
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srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
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parent = __zynq_clk_cpu_get_parent(srcsel);
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/* cpu clocks */
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clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
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clks[cpu_6or4x_clk].parent = parent;
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clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
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zynq_clk_get_rate(parent), div);
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clks[cpu_6or4x_clk].name = "cpu_6or4x";
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clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
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clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
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clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
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clks[cpu_3or2x_clk].name = "cpu_3or2x";
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clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
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clks[cpu_2x_clk].parent = cpu_6or4x_clk;
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clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
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(2 + clk_621);
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clks[cpu_2x_clk].name = "cpu_2x";
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clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
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clks[cpu_1x_clk].parent = cpu_6or4x_clk;
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clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
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(4 + 2 * clk_621);
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clks[cpu_1x_clk].name = "cpu_1x";
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}
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/**
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* periph_calc_two_divs() - Calculate clock dividers
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* @cur_rate: Current clock rate
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* @tgt_rate: Target clock rate
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* @prate: Parent clock rate
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* @div0: First divider (output)
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* @div1: Second divider (output)
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* Returns the actual clock rate possible.
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*
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* Calculates clock dividers for clocks with two 6-bit dividers.
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*/
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static unsigned long periph_calc_two_divs(unsigned long cur_rate,
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unsigned long tgt_rate, unsigned long prate, u32 *div0,
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u32 *div1)
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{
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long err, best_err = (long)(~0UL >> 1);
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unsigned long rate, best_rate = 0;
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u32 d0, d1;
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for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
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for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
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rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
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d1);
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err = abs(rate - tgt_rate);
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if (err < best_err) {
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*div0 = d0;
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*div1 = d1;
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best_err = err;
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best_rate = rate;
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}
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}
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}
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return best_rate;
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}
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/**
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* zynq_clk_periph_set_rate() - Set clock rate
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* @clk: Handle of the peripheral clock
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* @rate: New clock rate
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* Sets the clock frequency of @clk to @rate. Returns zero on success.
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*/
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static int zynq_clk_periph_set_rate(struct clk *clk,
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unsigned long rate)
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{
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u32 ctrl, div0 = 0, div1 = 0;
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unsigned long prate, new_rate, cur_rate = clk->frequency;
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ctrl = readl(clk->reg);
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prate = zynq_clk_get_rate(clk->parent);
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ctrl &= ~CLK_CTRL_DIV0_MASK;
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if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
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ctrl &= ~CLK_CTRL_DIV1_MASK;
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new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
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&div1);
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ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
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} else {
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div0 = DIV_ROUND_CLOSEST(prate, rate);
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div0 &= ZYNQ_CLK_MAXDIV;
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new_rate = DIV_ROUND_CLOSEST(rate, div0);
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}
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/* write new divs to hardware */
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ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
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writel(ctrl, clk->reg);
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/* update frequency in clk framework */
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clk->frequency = new_rate;
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return 0;
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}
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/**
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* zynq_clk_periph_get_rate() - Get clock rate
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* @clk: Handle of the peripheral clock
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* Returns the current clock rate of @clk.
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*/
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static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
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{
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u32 clk_ctrl = readl(clk->reg);
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u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
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u32 div1 = 1;
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if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
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div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
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/* a register value of zero == division by 1 */
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if (!div0)
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div0 = 1;
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if (!div1)
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div1 = 1;
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return
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DIV_ROUND_CLOSEST(
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DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
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div1);
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}
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/**
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* __zynq_clk_periph_get_parent() - Decode clock multiplexer
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* @srcsel: Mux select value
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* Returns the clock identifier associated with the selected mux input.
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*/
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static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
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{
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switch (srcsel) {
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case ZYNQ_CLKMUX_SEL_0:
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case ZYNQ_CLKMUX_SEL_1:
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return iopll_clk;
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case ZYNQ_CLKMUX_SEL_2:
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return armpll_clk;
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case ZYNQ_CLKMUX_SEL_3:
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return ddrpll_clk;
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default:
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return 0;
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}
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}
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/**
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* zynq_clk_periph_get_parent() - Decode clock multiplexer
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* @clk: Clock handle
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* Returns the clock identifier associated with the selected mux input.
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*/
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static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
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{
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u32 clk_ctrl = readl(clk->reg);
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u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
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return __zynq_clk_periph_get_parent(srcsel);
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}
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/**
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* zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
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* @clk: Pointer to struct clk for the clock
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* @ctrl: Clock control register
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* @name: PLL name
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* @two_divs: Indicates whether the clock features one or two dividers
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*/
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static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name,
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bool two_divs)
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{
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clk->name = name;
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clk->reg = ctrl;
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if (two_divs)
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clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
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clk->parent = zynq_clk_periph_get_parent(clk);
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clk->frequency = zynq_clk_periph_get_rate(clk);
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clk->ops.get_rate = zynq_clk_periph_get_rate;
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clk->ops.set_rate = zynq_clk_periph_set_rate;
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return 0;
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}
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static void init_periph_clocks(void)
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{
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zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl,
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"gem0", 1);
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zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl,
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"gem1", 1);
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zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl,
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"smc", 0);
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zynq_clk_register_periph_clk(&clks[lqspi_clk],
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&slcr_base->lqspi_clk_ctrl, "lqspi", 0);
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zynq_clk_register_periph_clk(&clks[sdio0_clk],
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&slcr_base->sdio_clk_ctrl, "sdio0", 0);
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zynq_clk_register_periph_clk(&clks[sdio1_clk],
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&slcr_base->sdio_clk_ctrl, "sdio1", 0);
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zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl,
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"spi0", 0);
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zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl,
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"spi1", 0);
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zynq_clk_register_periph_clk(&clks[uart0_clk],
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&slcr_base->uart_clk_ctrl, "uart0", 0);
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zynq_clk_register_periph_clk(&clks[uart1_clk],
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&slcr_base->uart_clk_ctrl, "uart1", 0);
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zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
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&slcr_base->dbg_clk_ctrl, "dbg_trc", 0);
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zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
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&slcr_base->dbg_clk_ctrl, "dbg_apb", 0);
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zynq_clk_register_periph_clk(&clks[pcap_clk],
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&slcr_base->pcap_clk_ctrl, "pcap", 0);
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zynq_clk_register_periph_clk(&clks[fclk0_clk],
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&slcr_base->fpga0_clk_ctrl, "fclk0", 1);
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zynq_clk_register_periph_clk(&clks[fclk1_clk],
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&slcr_base->fpga1_clk_ctrl, "fclk1", 1);
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zynq_clk_register_periph_clk(&clks[fclk2_clk],
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&slcr_base->fpga2_clk_ctrl, "fclk2", 1);
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zynq_clk_register_periph_clk(&clks[fclk3_clk],
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&slcr_base->fpga3_clk_ctrl, "fclk3", 1);
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}
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/**
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* zynq_clk_register_aper_clk() - Set up a APER clock with the framework
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* @clk: Pointer to struct clk for the clock
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* @ctrl: Clock control register
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* @name: PLL name
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*/
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static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name)
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{
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clk->name = name;
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clk->reg = ctrl;
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clk->parent = cpu_1x_clk;
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clk->frequency = zynq_clk_get_rate(clk->parent);
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}
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static void init_aper_clocks(void)
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{
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zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
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&slcr_base->aper_clk_ctrl, "usb0_aper");
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zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
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&slcr_base->aper_clk_ctrl, "usb1_aper");
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zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
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&slcr_base->aper_clk_ctrl, "gem0_aper");
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zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
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&slcr_base->aper_clk_ctrl, "gem1_aper");
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zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
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&slcr_base->aper_clk_ctrl, "sdio0_aper");
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zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
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&slcr_base->aper_clk_ctrl, "sdio1_aper");
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zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
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&slcr_base->aper_clk_ctrl, "spi0_aper");
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zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
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&slcr_base->aper_clk_ctrl, "spi1_aper");
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zynq_clk_register_aper_clk(&clks[can0_aper_clk],
|
|
&slcr_base->aper_clk_ctrl, "can0_aper");
|
|
zynq_clk_register_aper_clk(&clks[can1_aper_clk],
|
|
&slcr_base->aper_clk_ctrl, "can1_aper");
|
|
|
|
zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
|
|
&slcr_base->aper_clk_ctrl, "i2c0_aper");
|
|
zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
|
|
&slcr_base->aper_clk_ctrl, "i2c1_aper");
|
|
|
|
zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
|
|
&slcr_base->aper_clk_ctrl, "uart0_aper");
|
|
zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
|
|
&slcr_base->aper_clk_ctrl, "uart1_aper");
|
|
|
|
zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
|
|
&slcr_base->aper_clk_ctrl, "gpio_aper");
|
|
|
|
zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
|
|
&slcr_base->aper_clk_ctrl, "lqspi_aper");
|
|
|
|
zynq_clk_register_aper_clk(&clks[smc_aper_clk],
|
|
&slcr_base->aper_clk_ctrl, "smc_aper");
|
|
}
|
|
|
|
/**
|
|
* __zynq_clk_pll_get_rate() - Get PLL rate
|
|
* @addr: Address of the PLL's control register
|
|
* Returns the current PLL output rate.
|
|
*/
|
|
static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
|
|
{
|
|
u32 reg, mul, bypass;
|
|
|
|
reg = readl(addr);
|
|
bypass = reg & PLLCTRL_BPFORCE_MASK;
|
|
if (bypass)
|
|
mul = 1;
|
|
else
|
|
mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
|
|
|
|
return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
|
|
}
|
|
|
|
/**
|
|
* zynq_clk_pll_get_rate() - Get PLL rate
|
|
* @pll: Handle of the PLL
|
|
* Returns the current clock rate of @pll.
|
|
*/
|
|
static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
|
|
{
|
|
return __zynq_clk_pll_get_rate(pll->reg);
|
|
}
|
|
|
|
/**
|
|
* zynq_clk_register_pll() - Set up a PLL with the framework
|
|
* @clk: Pointer to struct clk for the PLL
|
|
* @ctrl: PLL control register
|
|
* @name: PLL name
|
|
* @prate: PLL input clock rate
|
|
*/
|
|
static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name,
|
|
unsigned long prate)
|
|
{
|
|
clk->name = name;
|
|
clk->reg = ctrl;
|
|
clk->frequency = zynq_clk_pll_get_rate(clk);
|
|
clk->ops.get_rate = zynq_clk_pll_get_rate;
|
|
}
|
|
|
|
/**
|
|
* clkid_2_register() - Get clock control register
|
|
* @id: Clock identifier of one of the PLLs
|
|
* Returns the address of the requested PLL's control register.
|
|
*/
|
|
static u32 *clkid_2_register(enum zynq_clk id)
|
|
{
|
|
switch (id) {
|
|
case armpll_clk:
|
|
return &slcr_base->arm_pll_ctrl;
|
|
case ddrpll_clk:
|
|
return &slcr_base->ddr_pll_ctrl;
|
|
case iopll_clk:
|
|
return &slcr_base->io_pll_ctrl;
|
|
default:
|
|
return &slcr_base->io_pll_ctrl;
|
|
}
|
|
}
|
|
|
|
/* API */
|
|
/**
|
|
* zynq_clk_early_init() - Early init for the clock framework
|
|
*
|
|
* This function is called from before relocation and sets up the CPU clock
|
|
* frequency in the global data struct.
|
|
*/
|
|
void zynq_clk_early_init(void)
|
|
{
|
|
u32 reg = readl(&slcr_base->arm_clk_ctrl);
|
|
u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
|
|
u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
|
|
enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
|
|
u32 *pllreg = clkid_2_register(parent);
|
|
unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
|
|
|
|
if (!div)
|
|
div = 1;
|
|
|
|
gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
|
|
}
|
|
|
|
/**
|
|
* get_uart_clk() - Get UART input frequency
|
|
* @dev_index: UART ID
|
|
* Returns UART input clock frequency in Hz.
|
|
*
|
|
* Compared to zynq_clk_get_rate() this function is designed to work before
|
|
* relocation and can be called when the serial UART is set up.
|
|
*/
|
|
unsigned long get_uart_clk(int dev_index)
|
|
{
|
|
u32 reg = readl(&slcr_base->uart_clk_ctrl);
|
|
u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
|
|
u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
|
|
enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
|
|
u32 *pllreg = clkid_2_register(parent);
|
|
unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
|
|
|
|
if (!div)
|
|
div = 1;
|
|
|
|
return DIV_ROUND_CLOSEST(prate, div);
|
|
}
|
|
|
|
/**
|
|
* set_cpu_clk_info() - Initialize clock framework
|
|
* Always returns zero.
|
|
*
|
|
* This function is called from common code after relocation and sets up the
|
|
* clock framework. The framework must not be used before this function had been
|
|
* called.
|
|
*/
|
|
int set_cpu_clk_info(void)
|
|
{
|
|
zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
|
|
"armpll", CONFIG_ZYNQ_PS_CLK_FREQ);
|
|
zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
|
|
"ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ);
|
|
zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
|
|
"iopll", CONFIG_ZYNQ_PS_CLK_FREQ);
|
|
|
|
init_ddr_clocks();
|
|
init_cpu_clocks();
|
|
init_periph_clocks();
|
|
init_aper_clocks();
|
|
|
|
gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
|
|
gd->bd->bi_dsp_freq = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* zynq_clk_get_rate() - Get clock rate
|
|
* @clk: Clock identifier
|
|
* Returns the current clock rate of @clk on success or zero for an invalid
|
|
* clock id.
|
|
*/
|
|
unsigned long zynq_clk_get_rate(enum zynq_clk clk)
|
|
{
|
|
if (clk < 0 || clk >= clk_max)
|
|
return 0;
|
|
|
|
return clks[clk].frequency;
|
|
}
|
|
|
|
/**
|
|
* zynq_clk_set_rate() - Set clock rate
|
|
* @clk: Clock identifier
|
|
* @rate: Requested clock rate
|
|
* Passes on the return value from the clock's set_rate() function or negative
|
|
* errno.
|
|
*/
|
|
int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
|
|
{
|
|
if (clk < 0 || clk >= clk_max)
|
|
return -ENODEV;
|
|
|
|
if (clks[clk].ops.set_rate)
|
|
return clks[clk].ops.set_rate(&clks[clk], rate);
|
|
|
|
return -ENXIO;
|
|
}
|
|
|
|
/**
|
|
* zynq_clk_get_name() - Get clock name
|
|
* @clk: Clock identifier
|
|
* Returns the name of @clk.
|
|
*/
|
|
const char *zynq_clk_get_name(enum zynq_clk clk)
|
|
{
|
|
return clks[clk].name;
|
|
}
|
|
|
|
/**
|
|
* soc_clk_dump() - Print clock frequencies
|
|
* Returns zero on success
|
|
*
|
|
* Implementation for the clk dump command.
|
|
*/
|
|
int soc_clk_dump(void)
|
|
{
|
|
int i;
|
|
|
|
printf("clk\t\tfrequency\n");
|
|
for (i = 0; i < clk_max; i++) {
|
|
const char *name = zynq_clk_get_name(i);
|
|
if (name)
|
|
printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
|
|
}
|
|
|
|
return 0;
|
|
}
|