401 lines
10 KiB
C
401 lines
10 KiB
C
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CONFIG_SYS_MEASURE_CPUCLK) || defined(DEBUG)
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#define PITC_SHIFT 16
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#define PITR_SHIFT 16
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/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
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#define SPEED_PIT_COUNTS 58
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#define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
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#define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
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/* Access functions for the Machine State Register */
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static __inline__ unsigned long get_msr(void)
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{
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unsigned long msr;
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asm volatile("mfmsr %0" : "=r" (msr) :);
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return msr;
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}
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static __inline__ void set_msr(unsigned long msr)
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{
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asm volatile("mtmsr %0" : : "r" (msr));
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Measure CPU clock speed (core clock GCLK1, GCLK2),
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* also determine bus clock speed (checking bus divider factor)
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*
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* (Approx. GCLK frequency in Hz)
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*
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* Initializes timer 2 and PIT, but disables them before return.
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* [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
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*
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* When measuring the CPU clock against the PIT, we count cpu clocks
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* for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
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* These strange values for the timing interval and prescaling are used
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* because the formula for the CPU clock is:
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*
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* CPU clock = count * (177 * (8192 / 58))
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*
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* = count * 24999.7241
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*
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* which is very close to
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*
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* = count * 25000
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*
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* Since the count gives the CPU clock divided by 25000, we can get
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* the CPU clock rounded to the nearest 0.1 MHz by
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*
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* CPU clock = ((count + 2) / 4) * 100000;
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*
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* The rounding is important since the measurement is sometimes going
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* to be high or low by 0.025 MHz, depending on exactly how the clocks
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* and counters interact. By rounding we get the exact answer for any
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* CPU clock that is an even multiple of 0.1 MHz.
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*/
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unsigned long measure_gclk(void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
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ulong timer2_val;
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ulong msr_val;
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#ifdef CONFIG_SYS_8XX_XIN
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/* dont use OSCM, only use EXTCLK/512 */
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immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
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#else
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immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
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#endif
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/* Reset + Stop Timer 2, no cascading
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*/
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timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);
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/* Keep stopped, halt in debug mode
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*/
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timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2);
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/* Timer 2 setup:
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* Output ref. interrupt disable, int. clock
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* Prescale by 177. Note that prescaler divides by value + 1
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* so we must subtract 1 here.
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*/
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timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
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timerp->cpmt_tcn2 = 0; /* reset state */
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timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
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/*
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* PIT setup:
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*
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* We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
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* so the count value would be SPEED_PITC_COUNTS - 1.
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* But there would be an uncertainty in the start time of 1/4
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* count since when we enable the PIT the count is not
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* synchronized to the 32768 Hz oscillator. The trick here is
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* to start the count higher and wait until the PIT count
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* changes to the required value before starting timer 2.
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*
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* One count high should be enough, but occasionally the start
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* is off by 1 or 2 counts of 32768 Hz. With the start value
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* set two counts high it seems very reliable.
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*/
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immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */
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immr->im_sit.sit_pitc = SPEED_PITC_INIT;
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immr->im_sitk.sitk_piscrk = KAPWR_KEY;
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immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
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/*
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* Start measurement - disable interrupts, just in case
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*/
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msr_val = get_msr ();
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set_msr (msr_val & ~MSR_EE);
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immr->im_sit.sit_piscr |= PISCR_PTE;
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/* spin until get exact count when we want to start */
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while (immr->im_sit.sit_pitr > SPEED_PITC);
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timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
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while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
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timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
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/* re-enable external interrupts if they were on */
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set_msr (msr_val);
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/* Disable timer and PIT
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*/
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timer2_val = timerp->cpmt_tcn2; /* save before reset timer */
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timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
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immr->im_sit.sit_piscr &= ~PISCR_PTE;
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#if defined(CONFIG_SYS_8XX_XIN)
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/* not using OSCM, using XIN, so scale appropriately */
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return (((timer2_val + 2) / 4) * (CONFIG_SYS_8XX_XIN/512))/8192 * 100000L;
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#else
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return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
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#endif
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}
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#endif
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void get_brgclk(uint sccr)
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{
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uint divider = 0;
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switch((sccr&SCCR_DFBRG11)>>11){
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case 0:
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divider = 1;
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break;
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case 1:
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divider = 4;
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break;
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case 2:
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divider = 16;
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break;
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case 3:
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divider = 64;
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break;
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}
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gd->arch.brg_clk = gd->cpu_clk/divider;
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}
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#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
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/*
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* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
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* or (if it is not defined) measure_gclk() (which uses the ref clock)
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* from above.
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*/
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int get_clocks (void)
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{
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uint immr = get_immr (0); /* Return full IMMR contents */
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volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
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uint sccr = immap->im_clkrst.car_sccr;
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/*
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* If for some reason measuring the gclk frequency won't
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* work, we return the hardwired value.
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* (For example, the cogent CMA286-60 CPU module has no
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* separate oscillator for PITRTCLK)
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*/
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#if defined(CONFIG_8xx_GCLK_FREQ)
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gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
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#elif defined(CONFIG_8xx_OSCLK)
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#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
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uint pll = immap->im_clkrst.car_plprcr;
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uint clk;
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if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
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clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
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(PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
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(1<<PLPRCR_val(S));
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} else {
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clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
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}
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if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */
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gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
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} else { /* High frequency division factor is used */
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gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
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}
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#else
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gd->cpu_clk = measure_gclk();
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#endif /* CONFIG_8xx_GCLK_FREQ */
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if ((sccr & SCCR_EBDF11) == 0) {
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/* No Bus Divider active */
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gd->bus_clk = gd->cpu_clk;
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} else {
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/* The MPC8xx has only one BDF: half clock speed */
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gd->bus_clk = gd->cpu_clk / 2;
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}
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get_brgclk(sccr);
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return (0);
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}
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#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */
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static long init_pll_866 (long clk);
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/* This function sets up PLL (init_pll_866() is called) and
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* fills gd->cpu_clk and gd->bus_clk according to the environment
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* variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
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* contains invalid value).
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* This functions requires an MPC866 or newer series CPU.
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*/
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int get_clocks_866 (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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char tmp[64];
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long cpuclk = 0;
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long sccr_reg;
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if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0)
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cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
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if ((CONFIG_SYS_8xx_CPUCLK_MIN > cpuclk) || (CONFIG_SYS_8xx_CPUCLK_MAX < cpuclk))
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cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
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gd->cpu_clk = init_pll_866 (cpuclk);
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#if defined(CONFIG_SYS_MEASURE_CPUCLK)
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gd->cpu_clk = measure_gclk ();
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#endif
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get_brgclk(immr->im_clkrst.car_sccr);
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/* if cpu clock <= 66 MHz then set bus division factor to 1,
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* otherwise set it to 2
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*/
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sccr_reg = immr->im_clkrst.car_sccr;
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sccr_reg &= ~SCCR_EBDF11;
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if (gd->cpu_clk <= 66000000) {
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sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
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gd->bus_clk = gd->cpu_clk;
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} else {
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sccr_reg |= SCCR_EBDF01; /* bus division factor = 2 */
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gd->bus_clk = gd->cpu_clk / 2;
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}
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immr->im_clkrst.car_sccr = sccr_reg;
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return (0);
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}
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/* Adjust sdram refresh rate to actual CPU clock.
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*/
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int sdram_adjust_866 (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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long mamr;
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mamr = immr->im_memctl.memc_mamr;
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mamr &= ~MAMR_PTA_MSK;
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mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
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immr->im_memctl.memc_mamr = mamr;
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return (0);
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}
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/* Configure PLL for MPC866/859/885 CPU series
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* PLL multiplication factor is set to the value nearest to the desired clk,
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* assuming a oscclk of 10 MHz.
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*/
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static long init_pll_866 (long clk)
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{
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extern void plprcr_write_866 (long);
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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long n, plprcr;
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char mfi, mfn, mfd, s, pdf;
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long step_mfi, step_mfn;
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if (clk < 20000000) {
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clk *= 2;
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pdf = 1;
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} else {
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pdf = 0;
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}
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if (clk < 40000000) {
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s = 2;
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step_mfi = CONFIG_8xx_OSCLK / 4;
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mfd = 7;
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step_mfn = CONFIG_8xx_OSCLK / 30;
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} else if (clk < 80000000) {
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s = 1;
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step_mfi = CONFIG_8xx_OSCLK / 2;
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mfd = 14;
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step_mfn = CONFIG_8xx_OSCLK / 30;
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} else {
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s = 0;
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step_mfi = CONFIG_8xx_OSCLK;
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mfd = 29;
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step_mfn = CONFIG_8xx_OSCLK / 30;
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}
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/* Calculate integer part of multiplication factor
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*/
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n = clk / step_mfi;
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mfi = (char)n;
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/* Calculate numerator of fractional part of multiplication factor
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*/
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n = clk - (n * step_mfi);
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mfn = (char)(n / step_mfn);
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/* Calculate effective clk
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*/
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n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1);
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immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
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plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
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| PLPRCR_MFD_MSK | PLPRCR_S_MSK
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| PLPRCR_MFI_MSK | PLPRCR_DBRMO
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| PLPRCR_PDF_MSK))
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| (mfn << PLPRCR_MFN_SHIFT)
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| (mfd << PLPRCR_MFD_SHIFT)
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| (s << PLPRCR_S_SHIFT)
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| (mfi << PLPRCR_MFI_SHIFT)
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| (pdf << PLPRCR_PDF_SHIFT);
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if( (mfn > 0) && ((mfd / mfn) > 10) )
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plprcr |= PLPRCR_DBRMO;
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plprcr_write_866 (plprcr); /* set value using SIU4/9 workaround */
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immr->im_clkrstk.cark_plprcrk = 0x00000000;
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return (n);
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}
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#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
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#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
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&& !defined(CONFIG_TQM885D)
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/*
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* Adjust sdram refresh rate to actual CPU clock
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* and set timebase source according to actual CPU clock
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*/
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int adjust_sdram_tbs_8xx (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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long mamr;
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long sccr;
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mamr = immr->im_memctl.memc_mamr;
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mamr &= ~MAMR_PTA_MSK;
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mamr |= ((gd->cpu_clk / CONFIG_SYS_PTA_PER_CLK) << MAMR_PTA_SHIFT);
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immr->im_memctl.memc_mamr = mamr;
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if (gd->cpu_clk < 67000000) {
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sccr = immr->im_clkrst.car_sccr;
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sccr |= SCCR_TBS;
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immr->im_clkrst.car_sccr = sccr;
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}
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return (0);
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}
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#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
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/* ------------------------------------------------------------------------- */
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