96 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			96 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  * (C) Copyright 2007-2009
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|  * Stefan Roese, DENX Software Engineering, sr@denx.de.
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #ifndef _4xx_i2c_h_
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| #define _4xx_i2c_h_
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| 
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| #define IIC_OK		0
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| #define IIC_NOK		1
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| #define IIC_NOK_LA	2		/* Lost arbitration */
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| #define IIC_NOK_ICT	3		/* Incomplete transfer */
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| #define IIC_NOK_XFRA	4		/* Transfer aborted */
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| #define IIC_NOK_DATA	5		/* No data in buffer */
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| #define IIC_NOK_TOUT	6		/* Transfer timeout */
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| 
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| #define IIC_TIMEOUT	1		/* 1 second */
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| 
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| struct ppc4xx_i2c {
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| 	u8 mdbuf;
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| 	u8 res1;
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| 	u8 sdbuf;
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| 	u8 res2;
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| 	u8 lmadr;
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| 	u8 hmadr;
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| 	u8 cntl;
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| 	u8 mdcntl;
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| 	u8 sts;
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| 	u8 extsts;
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| 	u8 lsadr;
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| 	u8 hsadr;
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| 	u8 clkdiv;
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| 	u8 intrmsk;
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| 	u8 xfrcnt;
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| 	u8 xtcntlss;
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| 	u8 directcntl;
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| 	u8 intr;
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| };
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| 
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| /* MDCNTL Register Bit definition */
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| #define IIC_MDCNTL_HSCL		0x01
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| #define IIC_MDCNTL_EUBS		0x02
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| #define IIC_MDCNTL_EINT		0x04
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| #define IIC_MDCNTL_ESM		0x08
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| #define IIC_MDCNTL_FSM		0x10
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| #define IIC_MDCNTL_EGC		0x20
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| #define IIC_MDCNTL_FMDB		0x40
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| #define IIC_MDCNTL_FSDB		0x80
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| 
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| /* CNTL Register Bit definition */
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| #define IIC_CNTL_PT		0x01
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| #define IIC_CNTL_READ		0x02
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| #define IIC_CNTL_CHT		0x04
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| #define IIC_CNTL_RPST		0x08
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| /* bit 2/3 for Transfer count*/
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| #define IIC_CNTL_AMD		0x40
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| #define IIC_CNTL_HMT		0x80
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| 
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| /* STS Register Bit definition */
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| #define IIC_STS_PT		0x01
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| #define IIC_STS_IRQA		0x02
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| #define IIC_STS_ERR		0x04
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| #define IIC_STS_SCMP		0x08
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| #define IIC_STS_MDBF		0x10
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| #define IIC_STS_MDBS		0x20
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| #define IIC_STS_SLPR		0x40
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| #define IIC_STS_SSS		0x80
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| 
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| /* EXTSTS Register Bit definition */
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| #define IIC_EXTSTS_XFRA		0x01
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| #define IIC_EXTSTS_ICT		0x02
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| #define IIC_EXTSTS_LA		0x04
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| #define IIC_EXTSTS_BCS_MASK	0x70
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| #define IIC_EXTSTS_BCS_FREE	0x40
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| 
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| /* XTCNTLSS Register Bit definition */
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| #define IIC_XTCNTLSS_SRST	0x01
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| #define IIC_XTCNTLSS_EPI	0x02
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| #define IIC_XTCNTLSS_SDBF	0x04
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| #define IIC_XTCNTLSS_SBDD	0x08
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| #define IIC_XTCNTLSS_SWS	0x10
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| #define IIC_XTCNTLSS_SWC	0x20
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| #define IIC_XTCNTLSS_SRS	0x40
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| #define IIC_XTCNTLSS_SRC	0x80
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| 
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| /* IICx_DIRECTCNTL register */
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| #define IIC_DIRCNTL_SDAC	0x08
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| #define IIC_DIRCNTL_SCC		0x04
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| #define IIC_DIRCNTL_MSDA	0x02
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| #define IIC_DIRCNTL_MSC		0x01
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| 
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| #define DIRCTNL_FREE(v)		(((v) & 0x0f) == 0x0f)
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| #endif
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