400 lines
11 KiB
C
400 lines
11 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot src/southbridge/intel/bd82x6x/pch.h
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_ARCH_PCH_H
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#define _ASM_ARCH_PCH_H
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#include <pci.h>
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/* PCH types */
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#define PCH_TYPE_CPT 0x1c /* CougarPoint */
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#define PCH_TYPE_PPT 0x1e /* IvyBridge */
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/* PCH stepping values for LPC device */
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#define PCH_STEP_A0 0
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#define PCH_STEP_A1 1
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#define PCH_STEP_B0 2
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#define PCH_STEP_B1 3
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#define PCH_STEP_B2 4
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#define PCH_STEP_B3 5
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#define DEFAULT_GPIOBASE 0x0480
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#define DEFAULT_PMBASE 0x0500
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#define SMBUS_IO_BASE 0x0400
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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/* PCI Configuration Space (D30:F0): PCI2PCI */
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#define PSTS 0x06
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#define SMLT 0x1b
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#define SECSTS 0x1e
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#define INTR 0x3c
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#define BCTRL 0x3e
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#define SBR (1 << 6)
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#define SEE (1 << 1)
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#define PERE (1 << 0)
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#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
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#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
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#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
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#define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
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#define PCH_PCIE_DEV_SLOT 28
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#define PCH_DEV PCI_BDF(0, 0, 0)
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#define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
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/* PCI Configuration Space (D31:F0): LPC */
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#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
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#define SERIRQ_CNTL 0x64
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#define GEN_PMCON_1 0xa0
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#define GEN_PMCON_2 0xa2
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#define GEN_PMCON_3 0xa4
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#define ETR3 0xac
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#define ETR3_CWORWRE (1 << 18)
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#define ETR3_CF9GR (1 << 20)
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/* GEN_PMCON_3 bits */
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#define RTC_BATTERY_DEAD (1 << 2)
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#define RTC_POWER_FAILED (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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#define BIOS_CNTL 0xDC
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#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
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#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
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#define GPIO_ROUT 0xb8
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#define PIRQA_ROUT 0x60
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#define PIRQB_ROUT 0x61
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#define PIRQC_ROUT 0x62
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#define PIRQD_ROUT 0x63
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#define PIRQE_ROUT 0x68
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#define PIRQF_ROUT 0x69
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#define PIRQG_ROUT 0x6A
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#define PIRQH_ROUT 0x6B
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#define GEN_PMCON_1 0xa0
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#define GEN_PMCON_2 0xa2
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#define GEN_PMCON_3 0xa4
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#define ETR3 0xac
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#define ETR3_CWORWRE (1 << 18)
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#define ETR3_CF9GR (1 << 20)
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#define PMBASE 0x40
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#define ACPI_CNTL 0x44
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#define BIOS_CNTL 0xDC
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#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
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#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
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#define GPIO_ROUT 0xb8
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/* PCI Configuration Space (D31:F1): IDE */
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#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
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#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
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#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
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#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
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#define IDE_SSDE1 (1 << 3)
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#define IDE_SSDE0 (1 << 2)
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#define IDE_PSDE1 (1 << 1)
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#define IDE_PSDE0 (1 << 0)
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#define IDE_SDMA_TIM 0x4a
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#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
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#define SIG_MODE_SEC_NORMAL (0 << 18)
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#define SIG_MODE_SEC_TRISTATE (1 << 18)
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#define SIG_MODE_SEC_DRIVELOW (2 << 18)
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#define SIG_MODE_PRI_NORMAL (0 << 16)
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#define SIG_MODE_PRI_TRISTATE (1 << 16)
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#define SIG_MODE_PRI_DRIVELOW (2 << 16)
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#define FAST_SCB1 (1 << 15)
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#define FAST_SCB0 (1 << 14)
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#define FAST_PCB1 (1 << 13)
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#define FAST_PCB0 (1 << 12)
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#define SCB1 (1 << 3)
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#define SCB0 (1 << 2)
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#define PCB1 (1 << 1)
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#define PCB0 (1 << 0)
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#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
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#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
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#define SATA_SP 0xd0 /* Scratchpad */
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/* SATA IOBP Registers */
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#define SATA_IOBP_SP0G3IR 0xea000151
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#define SATA_IOBP_SP1G3IR 0xea000051
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#define VCH 0x0000 /* 32bit */
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#define VCAP1 0x0004 /* 32bit */
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#define VCAP2 0x0008 /* 32bit */
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#define PVC 0x000c /* 16bit */
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#define PVS 0x000e /* 16bit */
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#define V0CAP 0x0010 /* 32bit */
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#define V0CTL 0x0014 /* 32bit */
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#define V0STS 0x001a /* 16bit */
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#define V1CAP 0x001c /* 32bit */
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#define V1CTL 0x0020 /* 32bit */
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#define V1STS 0x0026 /* 16bit */
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#define RCTCL 0x0100 /* 32bit */
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#define ESD 0x0104 /* 32bit */
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#define ULD 0x0110 /* 32bit */
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#define ULBA 0x0118 /* 64bit */
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#define RP1D 0x0120 /* 32bit */
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#define RP1BA 0x0128 /* 64bit */
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#define RP2D 0x0130 /* 32bit */
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#define RP2BA 0x0138 /* 64bit */
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#define RP3D 0x0140 /* 32bit */
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#define RP3BA 0x0148 /* 64bit */
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#define RP4D 0x0150 /* 32bit */
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#define RP4BA 0x0158 /* 64bit */
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#define HDD 0x0160 /* 32bit */
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#define HDBA 0x0168 /* 64bit */
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#define RP5D 0x0170 /* 32bit */
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#define RP5BA 0x0178 /* 64bit */
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#define RP6D 0x0180 /* 32bit */
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#define RP6BA 0x0188 /* 64bit */
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#define RPC 0x0400 /* 32bit */
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#define RPFN 0x0404 /* 32bit */
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#define TRSR 0x1e00 /* 8bit */
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#define TRCR 0x1e10 /* 64bit */
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#define TWDR 0x1e18 /* 64bit */
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#define IOTR0 0x1e80 /* 64bit */
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#define IOTR1 0x1e88 /* 64bit */
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#define IOTR2 0x1e90 /* 64bit */
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#define IOTR3 0x1e98 /* 64bit */
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#define TCTL 0x3000 /* 8bit */
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#define NOINT 0
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#define INTA 1
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#define INTB 2
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#define INTC 3
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#define INTD 4
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#define DIR_IDR 12 /* Interrupt D Pin Offset */
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#define DIR_ICR 8 /* Interrupt C Pin Offset */
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#define DIR_IBR 4 /* Interrupt B Pin Offset */
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#define DIR_IAR 0 /* Interrupt A Pin Offset */
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#define PIRQA 0
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#define PIRQB 1
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#define PIRQC 2
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#define PIRQD 3
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#define PIRQE 4
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#define PIRQF 5
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#define PIRQG 6
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#define PIRQH 7
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/* IO Buffer Programming */
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#define IOBPIRI 0x2330
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#define IOBPD 0x2334
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#define IOBPS 0x2338
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#define IOBPS_RW_BX ((1 << 9)|(1 << 10))
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#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
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#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
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#define D31IP 0x3100 /* 32bit */
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#define D31IP_TTIP 24 /* Thermal Throttle Pin */
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#define D31IP_SIP2 20 /* SATA Pin 2 */
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#define D31IP_SMIP 12 /* SMBUS Pin */
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#define D31IP_SIP 8 /* SATA Pin */
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#define D30IP 0x3104 /* 32bit */
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#define D30IP_PIP 0 /* PCI Bridge Pin */
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#define D29IP 0x3108 /* 32bit */
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#define D29IP_E1P 0 /* EHCI #1 Pin */
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#define D28IP 0x310c /* 32bit */
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#define D28IP_P8IP 28 /* PCI Express Port 8 */
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#define D28IP_P7IP 24 /* PCI Express Port 7 */
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#define D28IP_P6IP 20 /* PCI Express Port 6 */
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#define D28IP_P5IP 16 /* PCI Express Port 5 */
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#define D28IP_P4IP 12 /* PCI Express Port 4 */
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#define D28IP_P3IP 8 /* PCI Express Port 3 */
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#define D28IP_P2IP 4 /* PCI Express Port 2 */
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#define D28IP_P1IP 0 /* PCI Express Port 1 */
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#define D27IP 0x3110 /* 32bit */
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#define D27IP_ZIP 0 /* HD Audio Pin */
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#define D26IP 0x3114 /* 32bit */
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#define D26IP_E2P 0 /* EHCI #2 Pin */
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#define D25IP 0x3118 /* 32bit */
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#define D25IP_LIP 0 /* GbE LAN Pin */
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#define D22IP 0x3124 /* 32bit */
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#define D22IP_KTIP 12 /* KT Pin */
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#define D22IP_IDERIP 8 /* IDE-R Pin */
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#define D22IP_MEI2IP 4 /* MEI #2 Pin */
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#define D22IP_MEI1IP 0 /* MEI #1 Pin */
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#define D20IP 0x3128 /* 32bit */
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#define D20IP_XHCIIP 0
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#define D31IR 0x3140 /* 16bit */
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#define D30IR 0x3142 /* 16bit */
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#define D29IR 0x3144 /* 16bit */
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#define D28IR 0x3146 /* 16bit */
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#define D27IR 0x3148 /* 16bit */
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#define D26IR 0x314c /* 16bit */
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#define D25IR 0x3150 /* 16bit */
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#define D22IR 0x315c /* 16bit */
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#define D20IR 0x3160 /* 16bit */
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#define OIC 0x31fe /* 16bit */
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#define SPI_FREQ_SWSEQ 0x3893
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#define SPI_DESC_COMP0 0x38b0
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#define SPI_FREQ_WR_ERA 0x38b4
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#define DIR_ROUTE(a, b, c, d) \
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(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
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((b) << DIR_IBR) | ((a) << DIR_IAR))
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#define HPTC 0x3404 /* 32bit */
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#define BUC 0x3414 /* 32bit */
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#define PCH_DISABLE_GBE (1 << 5)
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#define FD 0x3418 /* 32bit */
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#define DISPBDF 0x3424 /* 16bit */
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#define FD2 0x3428 /* 32bit */
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#define CG 0x341c /* 32bit */
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/* Function Disable 1 RCBA 0x3418 */
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#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
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#define PCH_DISABLE_P2P (1 << 1)
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#define PCH_DISABLE_SATA1 (1 << 2)
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#define PCH_DISABLE_SMBUS (1 << 3)
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#define PCH_DISABLE_HD_AUDIO (1 << 4)
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#define PCH_DISABLE_EHCI2 (1 << 13)
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#define PCH_DISABLE_LPC (1 << 14)
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#define PCH_DISABLE_EHCI1 (1 << 15)
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#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
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#define PCH_DISABLE_THERMAL (1 << 24)
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#define PCH_DISABLE_SATA2 (1 << 25)
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#define PCH_DISABLE_XHCI (1 << 27)
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/* Function Disable 2 RCBA 0x3428 */
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#define PCH_DISABLE_KT (1 << 4)
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#define PCH_DISABLE_IDER (1 << 3)
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#define PCH_DISABLE_MEI2 (1 << 2)
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#define PCH_DISABLE_MEI1 (1 << 1)
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#define PCH_ENABLE_DBDF (1 << 0)
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/* ICH7 GPIOBASE */
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#define GPIO_USE_SEL 0x00
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#define GP_IO_SEL 0x04
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#define GP_LVL 0x0c
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#define GPO_BLINK 0x18
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#define GPI_INV 0x2c
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#define GPIO_USE_SEL2 0x30
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#define GP_IO_SEL2 0x34
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#define GP_LVL2 0x38
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#define GPIO_USE_SEL3 0x40
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#define GP_IO_SEL3 0x44
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#define GP_LVL3 0x48
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#define GP_RST_SEL1 0x60
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#define GP_RST_SEL2 0x64
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#define GP_RST_SEL3 0x68
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/* ICH7 PMBASE */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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#define PRBTNOR_STS (1 << 11)
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#define RTC_STS (1 << 10)
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#define PWRBTN_STS (1 << 8)
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#define GBL_STS (1 << 5)
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#define BM_STS (1 << 4)
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#define TMROF_STS (1 << 0)
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#define PM1_EN 0x02
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#define PCIEXPWAK_DIS (1 << 14)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define SLP_EN (1 << 13)
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#define SLP_TYP (7 << 10)
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#define SLP_TYP_S0 0
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#define SLP_TYP_S1 1
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#define SLP_TYP_S3 5
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#define SLP_TYP_S4 6
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#define SLP_TYP_S5 7
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#define GBL_RLS (1 << 2)
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#define BM_RLD (1 << 1)
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#define SCI_EN (1 << 0)
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#define PM1_TMR 0x08
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#define PROC_CNT 0x10
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#define LV2 0x14
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#define LV3 0x15
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#define LV4 0x16
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#define PM2_CNT 0x50 /* mobile only */
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#define GPE0_STS 0x20
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#define PME_B0_STS (1 << 13)
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#define PME_STS (1 << 11)
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#define BATLOW_STS (1 << 10)
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#define PCI_EXP_STS (1 << 9)
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#define RI_STS (1 << 8)
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#define SMB_WAK_STS (1 << 7)
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#define TCOSCI_STS (1 << 6)
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#define SWGPE_STS (1 << 2)
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#define HOT_PLUG_STS (1 << 1)
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#define GPE0_EN 0x28
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#define PME_B0_EN (1 << 13)
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#define PME_EN (1 << 11)
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#define TCOSCI_EN (1 << 6)
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#define SMI_EN 0x30
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#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
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#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
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#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
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#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
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#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
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#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
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#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
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#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
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#define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
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#define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
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#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
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#define EOS (1 << 1) /* End of SMI (deassert SMI#) */
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#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
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#define SMI_STS 0x34
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#define ALT_GP_SMI_EN 0x38
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#define ALT_GP_SMI_STS 0x3a
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#define GPE_CNTL 0x42
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#define DEVACT_STS 0x44
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#define SS_CNT 0x50
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#define C3_RES 0x54
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#define TCO1_STS 0x64
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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/**
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* pch_silicon_revision() - Read silicon device ID from the PCH
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*
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* @dev: PCH device
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* @return silicon device ID
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*/
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int pch_silicon_type(struct udevice *dev);
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/**
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* pch_pch_iobp_update() - Update a pch register
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*
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* @dev: PCH device
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* @address: Address to update
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* @andvalue: Value to AND with existing value
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* @orvalue: Value to OR with existing value
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*/
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void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
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u32 orvalue);
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#endif
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