124 lines
3.2 KiB
C
124 lines
3.2 KiB
C
/*
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* Copyright (c) 2011, Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef ASM_ARCH_PEI_DATA_H
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#define ASM_ARCH_PEI_DATA_H
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#include <linux/linkage.h>
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struct pch_usb3_controller_settings {
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/* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */
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uint16_t mode;
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/* 4 bit mask, 1: switchable, 0: not switchable */
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uint16_t hs_port_switch_mask;
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/* 0: No xHCI preOS driver, 1: xHCI preOS driver */
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uint16_t preboot_support;
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/* 0: Disable, 1: Enable */
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uint16_t xhci_streams;
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};
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typedef asmlinkage void (*tx_byte_func)(unsigned char byte);
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#define PEI_VERSION 6
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struct __packed pei_data {
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uint32_t pei_version;
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uint32_t mchbar;
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uint32_t dmibar;
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uint32_t epbar;
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uint32_t pciexbar;
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uint16_t smbusbar;
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uint32_t wdbbar;
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uint32_t wdbsize;
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uint32_t hpet_address;
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uint32_t rcba;
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uint32_t pmbase;
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uint32_t gpiobase;
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uint32_t thermalbase;
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uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */
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uint32_t tseg_size;
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uint8_t spd_addresses[4];
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uint8_t ts_addresses[4];
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int boot_mode;
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int ec_present;
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int gbe_enable;
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/*
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* 0 = leave channel enabled
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* 1 = disable dimm 0 on channel
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* 2 = disable dimm 1 on channel
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* 3 = disable dimm 0+1 on channel
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*/
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int dimm_channel0_disabled;
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int dimm_channel1_disabled;
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/* Seed values saved in CMOS */
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uint32_t scrambler_seed;
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uint32_t scrambler_seed_s3;
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/* Data read from flash and passed into MRC */
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unsigned char *mrc_input;
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unsigned int mrc_input_len;
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/* Data from MRC that should be saved to flash */
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unsigned char *mrc_output;
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unsigned int mrc_output_len;
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/*
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* Max frequency DDR3 could be ran at. Could be one of four values:
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* 800, 1067, 1333, 1600
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*/
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uint32_t max_ddr3_freq;
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/*
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* USB Port Configuration:
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* [0] = enable
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* [1] = overcurrent pin
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* [2] = length
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*
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* Ports 0-7 can be mapped to OC0-OC3
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* Ports 8-13 can be mapped to OC4-OC7
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*
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* Port Length
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* MOBILE:
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* < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
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* < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
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* DESKTOP:
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* < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
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* < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
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* < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
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*/
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uint16_t usb_port_config[16][3];
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/* See the usb3 struct above for details */
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struct pch_usb3_controller_settings usb3;
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/*
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* SPD data array for onboard RAM. Specify address 0xf0,
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* 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
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* spd_address for a given "DIMM".
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*/
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uint8_t spd_data[4][256];
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tx_byte_func tx_byte;
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int ddr3lv_support;
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/*
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* pcie_init needs to be set to 1 to have the system agent initialise
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* PCIe. Note: This should only be required if your system has Gen3
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* devices and it will increase your boot time by at least 100ms.
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*/
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int pcie_init;
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/*
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* N mode functionality. Leave this setting at 0.
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* 0 Auto
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* 1 1N
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* 2 2N
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*/
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int nmode;
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/*
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* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows
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* for DIMM SPD data to specify whether double-rate is required for
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* extended operating temperature range.
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* 0 Enable double rate based upon temperature thresholds
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* 1 Normal rate
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* 2 Always enable double rate
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*/
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int ddr_refresh_rate_config;
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};
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#endif
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