63 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
			
		
		
	
	
			63 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
| /*
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|  * (C) Copyright 2008
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|  * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com.
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <ppc_asm.tmpl>
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| #include <config.h>
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| #include <asm/mmu.h>
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| #include <asm/ppc4xx.h>
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| 
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| /**************************************************************************
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|  * TLB TABLE
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|  *
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|  * This table is used by the cpu boot code to setup the initial tlb
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|  * entries. Rather than make broad assumptions in the cpu source tree,
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|  * this table lets each board set things up however they like.
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|  *
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|  *  Pointer to the table is returned in r1
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|  *
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|  *************************************************************************/
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| 
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| 	.section .bootpg,"ax"
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| 	.globl tlbtab
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| tlbtab:
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| 	tlbtab_start
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| 
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| 	/*
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| 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
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| 	 * speed up boot process. It is patched after relocation to enable SA_I
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| 	 */
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| 	tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
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| 
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| 	/*
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| 	 * TLB entries for SDRAM are not needed on this platform.
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| 	 * They are dynamically generated in the SPD DDR(2) detection
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| 	 * routine.
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| 	 */
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| 
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| 	/* Although 512 KB, map 256k at a time */
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| 	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
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| 	tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I)
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| 
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| 	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
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| 
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| 	/*
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| 	 * Peripheral base
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| 	 */
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| 	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG)
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| 
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| 	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG)
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| 	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG)
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| 	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG)
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| 
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| 	tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG)
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| 	tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG)
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| 
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| 	tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG)
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| 	tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG)
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| 	tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG)
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| 	tlbtab_end
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