404 lines
8.8 KiB
C
404 lines
8.8 KiB
C
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* based on kilauea.c
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* by Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/ppc405.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/ppc4xx-gpio.h>
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#include <flash.h>
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#include <pca9698.h>
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#include "405ex.h"
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#include <gdsys_fpga.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <dtt.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PHYREG_CONTROL 0
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#define PHYREG_PAGE_ADDRESS 22
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#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
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#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
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#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17
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#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21
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#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
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#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300)
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enum {
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UNITTYPE_CCD_SWITCH = 1,
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};
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enum {
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HWVER_100 = 0,
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HWVER_110 = 1,
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};
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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static inline void blank_string(int size)
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{
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int i;
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for (i = 0; i < size; i++)
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putc('\b');
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for (i = 0; i < size; i++)
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putc(' ');
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for (i = 0; i < size; i++)
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putc('\b');
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}
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/*
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* Board early initialization function
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*/
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int misc_init_r(void)
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{
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/* startup fans */
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dtt_init();
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#ifdef CONFIG_ENV_IS_IN_FLASH
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/* Monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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#endif
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return 0;
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}
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static void print_fpga_info(unsigned dev)
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{
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u16 versions;
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u16 fpga_version;
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u16 fpga_features;
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int fpga_state = get_fpga_state(dev);
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unsigned unit_type;
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unsigned hardware_version;
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unsigned feature_channels;
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unsigned feature_expansion;
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FPGA_GET_REG(dev, versions, &versions);
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FPGA_GET_REG(dev, fpga_version, &fpga_version);
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FPGA_GET_REG(dev, fpga_features, &fpga_features);
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printf("FPGA%d: ", dev);
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if (fpga_state & FPGA_STATE_PLATFORM)
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printf("(legacy) ");
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if (fpga_state & FPGA_STATE_DONE_FAILED) {
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printf(" done timed out\n");
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return;
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}
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if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
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printf(" refelectione test failed\n");
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return;
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}
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unit_type = (versions & 0xf000) >> 12;
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hardware_version = versions & 0x000f;
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feature_channels = fpga_features & 0x007f;
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feature_expansion = fpga_features & (1<<15);
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switch (unit_type) {
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case UNITTYPE_CCD_SWITCH:
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printf("CCD-Switch");
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break;
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default:
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printf("UnitType %d(not supported)", unit_type);
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break;
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}
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switch (hardware_version) {
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case HWVER_100:
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printf(" HW-Ver 1.00\n");
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break;
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case HWVER_110:
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printf(" HW-Ver 1.10\n");
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break;
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default:
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printf(" HW-Ver %d(not supported)\n",
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hardware_version);
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break;
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}
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printf(" FPGA V %d.%02d, features:",
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fpga_version / 100, fpga_version % 100);
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printf(" %d channel(s)", feature_channels);
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printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: CATCenter Io64\n");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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return 0;
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}
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int configure_gbit_phy(char *bus, unsigned char addr)
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{
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unsigned short value;
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/* select page 0 */
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if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
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goto err_out;
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/* switch to powerdown */
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if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
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&value))
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goto err_out;
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if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
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value | 0x0004))
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goto err_out;
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/* select page 2 */
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if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
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goto err_out;
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/* disable SGMII autonegotiation */
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if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48))
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goto err_out;
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/* select page 0 */
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if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000))
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goto err_out;
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/* switch from powerdown to normal operation */
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if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
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&value))
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goto err_out;
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if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1,
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value & ~0x0004))
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goto err_out;
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/* reset phy so settings take effect */
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if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140))
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goto err_out;
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return 0;
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err_out:
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printf("Error writing to the PHY addr=%02x\n", addr);
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return -1;
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}
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int verify_gbit_phy(char *bus, unsigned char addr)
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{
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unsigned short value;
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/* select page 2 */
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if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002))
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goto err_out;
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/* verify SGMII link status */
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if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value))
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goto err_out;
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if (!(value & (1 << 10)))
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return -2;
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return 0;
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err_out:
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printf("Error writing to the PHY addr=%02x\n", addr);
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return -1;
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}
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int last_stage_init(void)
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{
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unsigned int k;
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unsigned int fpga;
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int failed = 0;
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char str_phys[] = "Setup PHYs -";
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char str_serdes[] = "Start SERDES blocks";
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char str_channels[] = "Start FPGA channels";
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char str_locks[] = "Verify SERDES locks";
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char str_hicb[] = "Verify HICB status";
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char str_status[] = "Verify PHY status -";
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char slash[] = "\\|/-\\|/-";
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print_fpga_info(0);
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print_fpga_info(1);
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/* setup Gbit PHYs */
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puts("TRANS: ");
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puts(str_phys);
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int retval;
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struct mii_dev *mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN);
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mdiodev->read = bb_miiphy_read;
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mdiodev->write = bb_miiphy_write;
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retval = mdio_register(mdiodev);
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if (retval < 0)
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return retval;
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for (k = 0; k < 32; ++k) {
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configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k);
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putc('\b');
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putc(slash[k % 8]);
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}
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mdiodev = mdio_alloc();
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if (!mdiodev)
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return -ENOMEM;
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strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN);
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mdiodev->read = bb_miiphy_read;
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mdiodev->write = bb_miiphy_write;
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retval = mdio_register(mdiodev);
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if (retval < 0)
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return retval;
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for (k = 0; k < 32; ++k) {
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configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k);
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putc('\b');
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putc(slash[k % 8]);
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}
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blank_string(strlen(str_phys));
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/* take fpga serdes blocks out of reset */
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puts(str_serdes);
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udelay(500000);
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FPGA_SET_REG(0, quad_serdes_reset, 0);
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FPGA_SET_REG(1, quad_serdes_reset, 0);
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blank_string(strlen(str_serdes));
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/* take channels out of reset */
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puts(str_channels);
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udelay(500000);
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for (fpga = 0; fpga < 2; ++fpga) {
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for (k = 0; k < 32; ++k)
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FPGA_SET_REG(fpga, ch[k].config_int, 0);
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}
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blank_string(strlen(str_channels));
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/* verify channels serdes lock */
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puts(str_locks);
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udelay(500000);
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for (fpga = 0; fpga < 2; ++fpga) {
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for (k = 0; k < 32; ++k) {
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u16 status;
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FPGA_GET_REG(fpga, ch[k].status_int, &status);
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if (!(status & (1 << 4))) {
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failed = 1;
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printf("fpga %d channel %d: no serdes lock\n",
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fpga, k);
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}
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/* reset events */
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FPGA_SET_REG(fpga, ch[k].status_int, 0);
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}
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}
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blank_string(strlen(str_locks));
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/* verify hicb_status */
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puts(str_hicb);
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for (fpga = 0; fpga < 2; ++fpga) {
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for (k = 0; k < 32; ++k) {
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u16 status;
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FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
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if (status)
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printf("fpga %d hicb %d: hicb status %04x\n",
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fpga, k, status);
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/* reset events */
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FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
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}
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}
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blank_string(strlen(str_hicb));
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/* verify phy status */
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puts(str_status);
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for (k = 0; k < 32; ++k) {
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if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) {
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printf("verify baseboard phy %d failed\n", k);
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failed = 1;
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}
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putc('\b');
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putc(slash[k % 8]);
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}
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for (k = 0; k < 32; ++k) {
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if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) {
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printf("verify extensionboard phy %d failed\n", k);
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failed = 1;
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}
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putc('\b');
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putc(slash[k % 8]);
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}
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blank_string(strlen(str_status));
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printf("Starting 64 channels %s\n", failed ? "failed" : "ok");
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return 0;
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}
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void gd405ex_init(void)
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{
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unsigned int k;
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if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
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} else {
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pca9698_direction_output(0x22, 39, 1);
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}
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}
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void gd405ex_set_fpga_reset(unsigned state)
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{
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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if (legacy) {
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if (state) {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
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} else {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
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}
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} else {
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pca9698_set_value(0x22, 39, state ? 0 : 1);
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}
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}
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void gd405ex_setup_hw(void)
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{
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gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0);
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gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1);
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}
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int gd405ex_get_fpga_done(unsigned fpga)
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{
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int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
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if (legacy)
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return in_le16((void *)LATCH3_BASE)
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& CONFIG_SYS_FPGA_DONE(fpga);
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else
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return pca9698_get_value(0x22, fpga ? 9 : 8);
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}
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