429 lines
9.6 KiB
C
429 lines
9.6 KiB
C
/*
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* (C) Copyright 2013
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/io.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <asm/fsl_law.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <pca9698.h>
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#include <watchdog.h>
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#include "../common/dp501.h"
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#include "controlcenterd-id.h"
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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HWVER_100 = 0,
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HWVER_110 = 1,
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HWVER_120 = 2,
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};
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struct ihs_fpga {
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u32 reflection_low; /* 0x0000 */
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u32 versions; /* 0x0004 */
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u32 fpga_version; /* 0x0008 */
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u32 fpga_features; /* 0x000c */
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u32 reserved[4]; /* 0x0010 */
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u32 control; /* 0x0020 */
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};
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#ifndef CONFIG_TRAILBLAZER
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static struct pci_device_id hydra_supported[] = {
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{ 0x6d5e, 0xcdc0 },
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{}
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};
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static void hydra_initialize(void);
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#endif
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
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/* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
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clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);
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/* Set pmuxcr to allow both i2c1 and i2c2 */
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setbits_be32(&gur->pmuxcr, 0x00001000);
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/* Set pmuxcr to enable GPIO 3_11-3_13 */
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setbits_be32(&gur->pmuxcr, 0x00000010);
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/* Set pmuxcr to enable GPIO 2_31,3_9+10 */
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setbits_be32(&gur->pmuxcr, 0x00000020);
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/* Set pmuxcr to enable GPIO 2_28-2_30 */
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setbits_be32(&gur->pmuxcr, 0x000000c0);
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/* Set pmuxcr to enable GPIO 3_20-3_22 */
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setbits_be32(&gur->pmuxcr2, 0x03000000);
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/* Set pmuxcr to enable IRQ0-2 */
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clrbits_be32(&gur->pmuxcr, 0x00000300);
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/* Set pmuxcr to disable IRQ3-11 */
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setbits_be32(&gur->pmuxcr, 0x000000F0);
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/* Read back the register to synchronize the write. */
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in_be32(&gur->pmuxcr);
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/* Set the pin muxing to enable ETSEC2. */
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clrbits_be32(&gur->pmuxcr2, 0x001F8000);
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#ifdef CONFIG_TRAILBLAZER
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/*
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* GPIO3_10 SPERRTRIGGER
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*/
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setbits_be32(&pgpio->gpdir, 0x00200000);
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clrbits_be32(&pgpio->gpdat, 0x00200000);
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udelay(100);
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setbits_be32(&pgpio->gpdat, 0x00200000);
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udelay(100);
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clrbits_be32(&pgpio->gpdat, 0x00200000);
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#endif
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/*
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* GPIO3_11 CPU-TO-FPGA-RESET#
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*/
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setbits_be32(&pgpio->gpdir, 0x00100000);
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clrbits_be32(&pgpio->gpdat, 0x00100000);
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/*
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* GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
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*/
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setbits_be32(&pgpio->gpdir, 0x00000400);
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: ControlCenter DIGITAL\n");
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return 0;
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}
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int misc_init_r(void)
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{
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return 0;
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}
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/*
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* A list of PCI and SATA slots
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*/
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enum slot_id {
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SLOT_PCIE1 = 1,
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SLOT_PCIE2,
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SLOT_PCIE3,
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SLOT_PCIE4,
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SLOT_PCIE5,
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SLOT_SATA1,
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SLOT_SATA2
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};
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/*
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* This array maps the slot identifiers to their names on the P1022DS board.
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*/
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static const char * const slot_names[] = {
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[SLOT_PCIE1] = "Slot 1",
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[SLOT_PCIE2] = "Slot 2",
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[SLOT_PCIE3] = "Slot 3",
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[SLOT_PCIE4] = "Slot 4",
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[SLOT_PCIE5] = "Mini-PCIe",
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[SLOT_SATA1] = "SATA 1",
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[SLOT_SATA2] = "SATA 2",
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};
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/*
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* This array maps a given SERDES configuration and SERDES device to the PCI or
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* SATA slot that it connects to. This mapping is hard-coded in the FPGA.
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*/
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static u8 serdes_dev_slot[][SATA2 + 1] = {
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[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
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[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
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[PCIE2] = SLOT_PCIE5 },
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[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3 },
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[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1c] = { [PCIE1] = SLOT_PCIE1,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
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[0x1f] = { [PCIE1] = SLOT_PCIE1 },
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};
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/*
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* Returns the name of the slot to which the PCIe or SATA controller is
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* connected
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*/
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const char *board_serdes_name(enum srds_prtcl device)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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enum slot_id slot = serdes_dev_slot[srds_cfg][device];
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const char *name = slot_names[slot];
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if (name)
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return name;
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else
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return "Nothing";
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}
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void hw_watchdog_reset(void)
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{
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
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clrbits_be32(&pgpio->gpdat, 0x00000400);
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setbits_be32(&pgpio->gpdat, 0x00000400);
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}
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#ifdef CONFIG_TRAILBLAZER
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int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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return run_command(getenv("bootcmd"), flag);
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}
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int board_early_init_r(void)
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{
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
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/*
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* GPIO3_12 PPC_SYSTEMREADY#
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*/
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setbits_be32(&pgpio->gpdir, 0x00080000);
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setbits_be32(&pgpio->gpodr, 0x00080000);
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clrbits_be32(&pgpio->gpdat, 0x00080000);
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return ccdm_compute_self_hash();
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}
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int last_stage_init(void)
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{
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startup_ccdm_id_module();
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return 0;
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}
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#else
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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hydra_initialize();
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}
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int board_early_init_r(void)
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{
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unsigned int k = 0;
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
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/* wait for FPGA configuration to finish */
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while (!pca9698_get_value(0x22, 11) && (k++ < 30))
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udelay(100000);
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if (k > 30) {
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puts("FPGA configuration timed out.\n");
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} else {
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/* clear FPGA reset */
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udelay(1000);
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setbits_be32(&pgpio->gpdat, 0x00100000);
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}
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/* give time for PCIe link training */
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udelay(100000);
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/*
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* GPIO3_12 PPC_SYSTEMREADY#
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*/
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setbits_be32(&pgpio->gpdir, 0x00080000);
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setbits_be32(&pgpio->gpodr, 0x00080000);
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clrbits_be32(&pgpio->gpdat, 0x00080000);
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return 0;
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}
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int last_stage_init(void)
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{
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/* Turn on Parade DP501 */
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pca9698_direction_output(0x22, 7, 1);
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udelay(500000);
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dp501_powerup(0x08);
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startup_ccdm_id_module();
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return 0;
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}
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/*
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* Initialize on-board and/or PCI Ethernet devices
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*
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* Returns:
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* <0, error
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* 0, no ethernet devices found
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* >0, number of ethernet devices initialized
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*/
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[2];
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unsigned int num = 0;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_HAS_FSL_DR_USB
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fdt_fixup_dr_usb(blob, bd);
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#endif
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FT_FSL_PCI_SETUP;
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return 0;
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}
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#endif
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static void hydra_initialize(void)
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{
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unsigned int i;
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pci_dev_t devno;
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/* Find and probe all the matching PCI devices */
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for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
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u32 val;
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struct ihs_fpga *fpga;
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u32 versions;
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u32 fpga_version;
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u32 fpga_features;
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unsigned hardware_version;
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unsigned feature_uart_channels;
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unsigned feature_sb_channels;
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/* Try to enable I/O accesses and bus-mastering */
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val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config_dword(devno, PCI_COMMAND, val);
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/* Make sure it worked */
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pci_read_config_dword(devno, PCI_COMMAND, &val);
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if (!(val & PCI_COMMAND_MEMORY)) {
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puts("Can't enable I/O memory\n");
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continue;
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}
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if (!(val & PCI_COMMAND_MASTER)) {
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puts("Can't enable bus-mastering\n");
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continue;
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}
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/* read FPGA details */
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fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
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PCI_REGION_MEM);
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/* disable sideband clocks */
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writel(1, &fpga->control);
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versions = readl(&fpga->versions);
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fpga_version = readl(&fpga->fpga_version);
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fpga_features = readl(&fpga->fpga_features);
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hardware_version = versions & 0xf;
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feature_uart_channels = (fpga_features >> 6) & 0x1f;
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feature_sb_channels = fpga_features & 0x1f;
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printf("FPGA%d: ", i);
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switch (hardware_version) {
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case HWVER_100:
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printf("HW-Ver 1.00\n");
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break;
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case HWVER_110:
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printf("HW-Ver 1.10\n");
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break;
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case HWVER_120:
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printf("HW-Ver 1.20\n");
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break;
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default:
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printf("HW-Ver %d(not supported)\n",
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hardware_version);
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break;
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}
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printf(" FPGA V %d.%02d, features:",
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fpga_version / 100, fpga_version % 100);
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printf(" %d uart channel(s)", feature_uart_channels);
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printf(" %d sideband channel(s)\n", feature_sb_channels);
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}
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}
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#endif
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