434 lines
15 KiB
C
434 lines
15 KiB
C
/*
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* (C) Copyright 2001
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Adapted for PATI
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*/
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#include <common.h>
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#include <command.h>
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#define PLX9056_LOC
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#include "plx9056.h"
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#include "pati.h"
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#include "pci_eeprom.h"
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extern void show_pld_regs(void);
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extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
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extern void user_led0(int led_on);
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extern void user_led1(int led_on);
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_SYS_PCI_CON_DEVICE)
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extern void pci_con_disc(void);
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extern void pci_con_connect(void);
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#endif
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/******************************************************************************
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* Eeprom Support
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******************************************************************************/
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unsigned long get32(unsigned long addr)
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{
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unsigned long *p=(unsigned long *)addr;
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return *p;
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}
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void set32(unsigned long addr,unsigned long data)
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{
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unsigned long *p=(unsigned long *)addr;
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*p=data;
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}
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#define PCICFG_GET_REG(x) (get32((x) + PCI_CONFIG_BASE))
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#define PCICFG_SET_REG(x,y) (set32((x) + PCI_CONFIG_BASE,(y)))
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/******************************************************************************
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* reload_pci_eeprom
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******************************************************************************/
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static void reload_pci_eeprom(void)
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{
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unsigned long reg;
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/* Set Bit 29 and clear it again */
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reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
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udelay(1);
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/* set it*/
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reg|=(1<<29);
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
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/* EECLK @ 33MHz = 125kHz
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* -> extra long load = 32 * 16bit = 512Bit @ 125kHz = 4.1msec
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* use 20msec
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*/
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udelay(20000); /* wait 20ms */
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reg &= ~(1<<29); /* set it low */
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
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udelay(1); /* wait some time */
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}
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/******************************************************************************
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* clock_pci_eeprom
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******************************************************************************/
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static void clock_pci_eeprom(void)
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{
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unsigned long reg;
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/* clock is low, data is valid */
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reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
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udelay(1);
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/* set clck high */
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reg|=(1<<24);
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
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udelay(1); /* wait some time */
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reg &= ~(1<<24); /* set clock low */
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
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udelay(1); /* wait some time */
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}
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/******************************************************************************
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* send_pci_eeprom_cmd
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******************************************************************************/
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static void send_pci_eeprom_cmd(unsigned long cmd, unsigned char len)
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{
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unsigned long reg;
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int i;
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reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
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/* Clear all EEPROM bits */
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reg &= ~(0xF << 24);
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/* Toggle EEPROM's Chip select to get it out of Shift Register Mode */
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
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udelay(1); /* wait some time */
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/* Enable EEPROM Chip Select */
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reg |= (1 << 25);
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
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/* Send EEPROM command - one bit at a time */
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for (i = (int)(len-1); i >= 0; i--) {
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/* Check if current bit is 0 or 1 */
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if (cmd & (1 << i))
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
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else
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg);
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clock_pci_eeprom();
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}
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}
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/******************************************************************************
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* write_pci_eeprom_offs
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******************************************************************************/
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static void write_pci_eeprom_offs(unsigned short offset, unsigned short value)
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{
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unsigned long reg;
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int bitpos, cmdshft, cmdlen, timeout;
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/* we're using the Eeprom 93CS66 */
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cmdshft = 2;
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cmdlen = EE66_CMD_LEN;
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/* Send Write_Enable command to EEPROM */
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send_pci_eeprom_cmd((EE_WREN << cmdshft),cmdlen);
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/* Send EEPROM Write command and offset to EEPROM */
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send_pci_eeprom_cmd((EE_WRITE << cmdshft) | (offset / 2),cmdlen);
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reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
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/* Clear all EEPROM bits */
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reg &= ~(0xF << 24);
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/* Make sure EEDO Input is disabled for some PLX chips */
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reg &= ~(1 << 31);
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/* Enable EEPROM Chip Select */
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reg |= (1 << 25);
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/* Write 16-bit value to EEPROM - one bit at a time */
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for (bitpos = 15; bitpos >= 0; bitpos--) {
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/* Get bit value and shift into result */
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if (value & (1 << bitpos))
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,(reg | (1<<26)));
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else
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg );
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clock_pci_eeprom();
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} /* for */
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/* Deselect Chip */
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(1 << 25));
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/* Re-select Chip */
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 25));
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/* A small delay is needed to let EEPROM complete */
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timeout = 0;
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do {
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udelay(10);
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reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
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timeout++;
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} while (((reg & (1 << 27)) == 0) && timeout < 20000);
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/* Send Write_Disable command to EEPROM */
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send_pci_eeprom_cmd((EE_WDS << cmdshft),cmdlen);
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/* Clear Chip Select and all other EEPROM bits */
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
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}
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/******************************************************************************
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* read_pci_eeprom_offs
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******************************************************************************/
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static void read_pci_eeprom_offs(unsigned short offset, unsigned short *pvalue)
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{
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unsigned long reg;
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int bitpos, cmdshft, cmdlen;
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/* we're using the Eeprom 93CS66 */
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cmdshft = 2;
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cmdlen = EE66_CMD_LEN;
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/* Send EEPROM read command and offset to EEPROM */
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send_pci_eeprom_cmd((EE_READ << cmdshft) | (offset / 2),cmdlen);
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/* Set EEPROM write output bit */
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reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
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/* Set EEDO Input enable */
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reg |= (1 << 31);
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg | (1 << 26));
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/* Get 16-bit value from EEPROM - one bit at a time */
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for (bitpos = 0; bitpos < 16; bitpos++) {
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clock_pci_eeprom();
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udelay(10);
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reg=PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT);
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/* Get bit value and shift into result */
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if (reg & (1 << 27))
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*pvalue = (unsigned short)((*pvalue << 1) | 1);
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else
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*pvalue = (unsigned short)(*pvalue << 1);
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}
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/* Clear EEDO Input enable */
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reg &= ~(1 << 31);
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/* Clear Chip Select and all other EEPROM bits */
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PCICFG_SET_REG(PCI9056_EEPROM_CTRL_STAT,reg & ~(0xF << 24));
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}
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/******************************************************************************
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* EEPROM read/writes
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******************************************************************************/
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#undef EEPROM_DBG
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static int pati_pci_eeprom_erase(void)
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{
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int i;
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printf("Erasing EEPROM ");
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for( i=0; i < PATI_EEPROM_LAST_OFFSET; i+=2) {
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write_pci_eeprom_offs(i,0xffff);
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if((i%0x10))
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printf(".");
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}
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printf("\nDone\n");
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return 0;
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}
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static int pati_pci_eeprom_prg(void)
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{
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int i;
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i=0;
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printf("Programming EEPROM ");
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while(pati_eeprom[i].offset<0xffff) {
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write_pci_eeprom_offs(pati_eeprom[i].offset,pati_eeprom[i].value);
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#ifdef EEPROM_DBG
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printf("0x%04X: 0x%04X\n",pati_eeprom[i].offset, pati_eeprom[i].value);
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#else
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if((i%0x10))
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printf(".");
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#endif
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i++;
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}
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printf("\nDone\n");
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return 0;
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}
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static int pati_pci_eeprom_write(unsigned short offset, unsigned long addr, unsigned short size)
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{
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int i;
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unsigned short value;
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unsigned short *buffer =(unsigned short *)addr;
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if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
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size = PATI_EEPROM_LAST_OFFSET - offset;
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}
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printf("Write To EEPROM from 0x%lX to 0x%X 0x%X words\n", addr, offset, size/2);
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for( i = offset; i< (offset + size); i+=2) {
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value = *buffer++;
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write_pci_eeprom_offs(i,value);
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#ifdef EEPROM_DBG
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printf("0x%04X: 0x%04X\n",i, value);
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#else
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if((i%0x10))
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printf(".");
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#endif
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}
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printf("\nDone\n");
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return 0;
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}
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static int pati_pci_eeprom_read(unsigned short offset, unsigned long addr, unsigned short size)
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{
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int i;
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unsigned short value = 0;
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unsigned short *buffer =(unsigned short *)addr;
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if((offset + size) > PATI_EEPROM_LAST_OFFSET) {
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size = PATI_EEPROM_LAST_OFFSET - offset;
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}
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printf("Read from EEPROM from 0x%X to 0x%lX 0x%X words\n", offset, addr, size/2);
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for( i = offset; i< (offset + size); i+=2) {
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read_pci_eeprom_offs(i,&value);
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*buffer++=value;
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#ifdef EEPROM_DBG
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printf("0x%04X: 0x%04X\n",i, value);
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#else
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if((i%0x10))
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printf(".");
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#endif
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}
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printf("\nDone\n");
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return 0;
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}
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/******************************************************************************
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* PCI Bridge Registers Dump
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*******************************************************************************/
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static void display_pci_regs(void)
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{
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printf(" PCI9056_SPACE0_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_RANGE));
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printf(" PCI9056_SPACE0_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_REMAP));
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printf(" PCI9056_LOCAL_DMA_ARBIT %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_DMA_ARBIT));
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printf(" PCI9056_ENDIAN_DESC %08lX\n",PCICFG_GET_REG(PCI9056_ENDIAN_DESC));
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printf(" PCI9056_EXP_ROM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_RANGE));
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printf(" PCI9056_EXP_ROM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_REMAP));
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printf(" PCI9056_SPACE0_ROM_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE0_ROM_DESC));
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printf(" PCI9056_DM_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_DM_RANGE));
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printf(" PCI9056_DM_MEM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_MEM_BASE));
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printf(" PCI9056_DM_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_DM_IO_BASE));
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printf(" PCI9056_DM_PCI_MEM_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_MEM_REMAP));
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printf(" PCI9056_DM_PCI_IO_CONFIG %08lX\n",PCICFG_GET_REG(PCI9056_DM_PCI_IO_CONFIG));
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printf(" PCI9056_SPACE1_RANGE %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_RANGE));
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printf(" PCI9056_SPACE1_REMAP %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_REMAP));
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printf(" PCI9056_SPACE1_DESC %08lX\n",PCICFG_GET_REG(PCI9056_SPACE1_DESC));
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printf(" PCI9056_DM_DAC %08lX\n",PCICFG_GET_REG(PCI9056_DM_DAC));
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printf(" PCI9056_MAILBOX0 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX0));
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printf(" PCI9056_MAILBOX1 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX1));
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printf(" PCI9056_MAILBOX2 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX2));
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printf(" PCI9056_MAILBOX3 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX3));
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printf(" PCI9056_MAILBOX4 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX4));
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printf(" PCI9056_MAILBOX5 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX5));
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printf(" PCI9056_MAILBOX6 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX6));
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printf(" PCI9056_MAILBOX7 %08lX\n",PCICFG_GET_REG(PCI9056_MAILBOX7));
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printf(" PCI9056_PCI_TO_LOC_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_PCI_TO_LOC_DBELL));
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printf(" PCI9056_LOC_TO_PCI_DBELL %08lX\n",PCICFG_GET_REG(PCI9056_LOC_TO_PCI_DBELL));
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printf(" PCI9056_INT_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_INT_CTRL_STAT));
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printf(" PCI9056_EEPROM_CTRL_STAT %08lX\n",PCICFG_GET_REG(PCI9056_EEPROM_CTRL_STAT));
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printf(" PCI9056_PERM_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_PERM_VENDOR_ID));
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printf(" PCI9056_REVISION_ID %08lX\n",PCICFG_GET_REG(PCI9056_REVISION_ID));
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printf(" \n");
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printf(" PCI9056_VENDOR_ID %08lX\n",PCICFG_GET_REG(PCI9056_VENDOR_ID));
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printf(" PCI9056_COMMAND %08lX\n",PCICFG_GET_REG(PCI9056_COMMAND));
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printf(" PCI9056_REVISION %08lX\n",PCICFG_GET_REG(PCI9056_REVISION));
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printf(" PCI9056_CACHE_SIZE %08lX\n",PCICFG_GET_REG(PCI9056_CACHE_SIZE));
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printf(" PCI9056_RTR_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_BASE));
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printf(" PCI9056_RTR_IO_BASE %08lX\n",PCICFG_GET_REG(PCI9056_RTR_IO_BASE));
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printf(" PCI9056_LOCAL_BASE0 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE0));
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printf(" PCI9056_LOCAL_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_LOCAL_BASE1));
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printf(" PCI9056_UNUSED_BASE1 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE1));
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printf(" PCI9056_UNUSED_BASE2 %08lX\n",PCICFG_GET_REG(PCI9056_UNUSED_BASE2));
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printf(" PCI9056_CIS_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CIS_PTR));
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printf(" PCI9056_SUB_ID %08lX\n",PCICFG_GET_REG(PCI9056_SUB_ID));
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printf(" PCI9056_EXP_ROM_BASE %08lX\n",PCICFG_GET_REG(PCI9056_EXP_ROM_BASE));
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printf(" PCI9056_CAP_PTR %08lX\n",PCICFG_GET_REG(PCI9056_CAP_PTR));
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printf(" PCI9056_INT_LINE %08lX\n",PCICFG_GET_REG(PCI9056_INT_LINE));
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printf(" PCI9056_PM_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_PM_CAP_ID));
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printf(" PCI9056_PM_CSR %08lX\n",PCICFG_GET_REG(PCI9056_PM_CSR));
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printf(" PCI9056_HS_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_HS_CAP_ID));
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printf(" PCI9056_VPD_CAP_ID %08lX\n",PCICFG_GET_REG(PCI9056_VPD_CAP_ID));
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printf(" PCI9056_VPD_DATA %08lX\n",PCICFG_GET_REG(PCI9056_VPD_DATA));
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}
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int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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if (strcmp(argv[1], "info") == 0)
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{
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show_pld_regs();
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return 0;
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}
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if (strcmp(argv[1], "pci") == 0)
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{
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display_pci_regs();
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return 0;
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}
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if (strcmp(argv[1], "led") == 0)
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{
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int led_nr,led_on;
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led_nr = (int)simple_strtoul(argv[2], NULL, 10);
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led_on = (int)simple_strtoul(argv[3], NULL, 10);
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if(!led_nr)
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user_led0(led_on);
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else
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user_led1(led_on);
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return 0;
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}
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#if defined(CONFIG_SYS_PCI_CON_DEVICE)
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if (strcmp(argv[1], "con") == 0) {
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pci_con_connect();
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return 0;
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}
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if (strcmp(argv[1], "disc") == 0) {
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pci_con_disc();
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return 0;
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}
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#endif
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if (strcmp(argv[1], "eeprom") == 0) {
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unsigned long addr;
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int size, offset;
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offset = 0;
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size = PATI_EEPROM_LAST_OFFSET;
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if(argc>2) {
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if(argc>3) {
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addr = simple_strtoul(argv[3], NULL, 16);
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if(argc>4)
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offset = (int) simple_strtoul(argv[4], NULL, 16);
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if(argc>5)
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size = (int) simple_strtoul(argv[5], NULL, 16);
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if (strcmp(argv[2], "read") == 0) {
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return (pati_pci_eeprom_read(offset, addr, size));
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}
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if (strcmp(argv[2], "write") == 0) {
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return (pati_pci_eeprom_write(offset, addr, size));
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}
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}
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if (strcmp(argv[2], "prg") == 0) {
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return (pati_pci_eeprom_prg());
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}
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if (strcmp(argv[2], "era") == 0) {
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return (pati_pci_eeprom_erase());
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}
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if (strcmp(argv[2], "reload") == 0) {
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reload_pci_eeprom();
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return 0;
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}
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}
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}
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return (do_mplcommon(cmdtp, flag, argc, argv));
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}
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U_BOOT_CMD(
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pati, 8, 1, do_pati,
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"PATI specific Cmds",
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"info - displays board information\n"
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"pati pci - displays PCI registers\n"
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"pati led <nr> <on> \n"
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" - switch LED <nr> <on>\n"
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"pati flash mem [SrcAddr]\n"
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" - updates U-Boot with image in memory\n"
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"pati eeprom <cmd> - PCI EEPROM sub-system\n"
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" read <addr> <offset> <size>\n"
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" - read PCI EEPROM to <addr> from <offset> <size> words\n"
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" write <addr> <offset> <size>\n"
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" - write PCI EEPROM from <addr> to <offset> <size> words\n"
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" prg - programm PCI EEPROM with default values\n"
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" era - erase PCI EEPROM (write all word to 0xffff)\n"
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" reload- Reload PCI Bridge with EEPROM Values\n"
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" NOTE: <addr> must start on word boundary\n"
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" <offset> and <size> must be even byte values"
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);
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/* ------------------------------------------------------------------------- */
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