132 lines
6.5 KiB
C
132 lines
6.5 KiB
C
/*
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* (C) Copyright 2001
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/****************************************************************************
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* Global routines used for PIP405
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*****************************************************************************/
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#ifndef __ASSEMBLY__
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extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
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void print_pip405_info(void);
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void user_led0(unsigned char on);
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void user_led1(unsigned char on);
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#define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800
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#define PLD_PART_REG PLD_BASE_ADDRESS + 0
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#define PLD_VERS_REG PLD_BASE_ADDRESS + 1
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#define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2
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#define PLD_LED_USER_REG PLD_BASE_ADDRESS + 3
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#define PLD_SYS_MAN_REG PLD_BASE_ADDRESS + 4
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#define PLD_FLASH_COM_REG PLD_BASE_ADDRESS + 5
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#define PLD_CAN_REG PLD_BASE_ADDRESS + 6
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#define PLD_SER_PWR_REG PLD_BASE_ADDRESS + 7
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#define PLD_COM_PWR_REG PLD_BASE_ADDRESS + 8
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#define PLD_NIC_VGA_REG PLD_BASE_ADDRESS + 9
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#define PLD_SCSI_RST_REG PLD_BASE_ADDRESS + 0xA
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#define PIIX4_VENDOR_ID 0x8086
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#define PIIX4_IDE_DEV_ID 0x7111
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#endif
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/* timings */
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/* CS Config register (CS7) */
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#define CONFIG_PORT_BME 0 /* Burst disable */
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#define CONFIG_PORT_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
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#define CONFIG_PORT_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
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#define CONFIG_PORT_OEN 1 /* Cycles from CS low to OE low */
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#define CONFIG_PORT_WBN 1 /* Cycles from CS low to WE low */
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#define CONFIG_PORT_WBF 1 /* Cycles from WE high to CS high */
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#define CONFIG_PORT_TH 2 /* Number of hold cycles after transfer */
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#define CONFIG_PORT_RE 0 /* Ready disabled */
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#define CONFIG_PORT_SOR 1 /* Sample on Ready disabled */
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#define CONFIG_PORT_BEM 0 /* Byte Write only active on Write cycles */
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#define CONFIG_PORT_PEN 0 /* Parity disable */
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#define CONFIG_PORT_AP ((CONFIG_PORT_BME << 31) + (CONFIG_PORT_TWE << 23) + (CONFIG_PORT_CSN << 18) + (CONFIG_PORT_OEN << 16) + (CONFIG_PORT_WBN << 14) + \
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(CONFIG_PORT_WBF << 12) + (CONFIG_PORT_TH << 9) + (CONFIG_PORT_RE << 8) + (CONFIG_PORT_SOR << 7) + (CONFIG_PORT_BEM << 6) + (CONFIG_PORT_PEN << 5))
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define CONFIG_PORT_BS 0 /* 1 MByte */
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/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
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#define CONFIG_PORT_BU 3 /* R/W */
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/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
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#define CONFIG_PORT_BW 0 /* 16Bit */
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#define CONFIG_PORT_CR ((CONFIG_PORT_ADDR & 0xfff00000) + (CONFIG_PORT_BS << 17) + (CONFIG_PORT_BU << 15) + (CONFIG_PORT_BW << 13))
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/* Flash CS0 or CS 1 */
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/* 0x7F8FFE80 slowest timing at all... */
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#define FLASH_BME_B 1 /* Burst enable */
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#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
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#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
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#define FLASH_BME 0 /* Burst disable */
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#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
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#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
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#define FLASH_OEN 1 /* Cycles from CS low to OE low */
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#define FLASH_WBN 1 /* Cycles from CS low to WE low */
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#define FLASH_WBF 1 /* Cycles from WE high to CS high */
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#define FLASH_TH 2 /* Number of hold cycles after transfer */
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#define FLASH_RE 0 /* Ready disabled */
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#define FLASH_SOR 1 /* Sample on Ready disabled */
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#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
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#define FLASH_PEN 0 /* Parity disable */
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/* Access Parameter Register for non Boot */
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#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
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(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
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/* Access Parameter Register for Boot */
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#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
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(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
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/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
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#define FLASH_BU 3 /* R/W */
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/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
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#define FLASH_BW 1 /* 16Bit */
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/* CR register for Boot */
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#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
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/* CR register for non Boot */
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#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
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/* MPS CS1 or CS0 */
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/* Boot CS: */
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#define MPS_BME_B 1 /* Burst enable */
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#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
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#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
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#define MPS_BME 0 /* Burst disable */
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#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
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#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
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#define MPS_OEN 1 /* Cycles from CS low to OE low */
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#define MPS_WBN 1 /* Cycles from CS low to WE low */
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#define MPS_WBF 1 /* Cycles from WE high to CS high */
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#define MPS_TH 2 /* Number of hold cycles after transfer */
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#define MPS_RE 0 /* Ready disabled */
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#define MPS_SOR 1 /* Sample on Ready disabled */
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#define MPS_BEM 0 /* Byte Write only active on Write cycles */
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#define MPS_PEN 0 /* Parity disable */
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/* Access Parameter Register for non Boot */
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#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
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(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
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/* Access Parameter Register for Boot */
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#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
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(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define MPS_BS 2 /* 4 MByte */
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#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
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/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
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#define MPS_BU 3 /* R/W */
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/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
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#define MPS_BW 0 /* 8Bit */
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/* CR register for Boot */
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#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
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/* CR register for non Boot */
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#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
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