103 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			103 lines
		
	
	
		
			2.7 KiB
		
	
	
	
		
			C
		
	
	
	
| /*
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|  * drivers/usb/gadget/dwc2_udc_otg.c
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|  * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
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|  *
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|  * Copyright (C) 2008 for Samsung Electronics
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|  *
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|  * BSP Support for Samsung's UDC driver
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|  * available at:
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|  * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
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|  *
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|  * State machine bugfixes:
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|  * Marek Szyprowski <m.szyprowski@samsung.com>
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|  *
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|  * Ported to u-boot:
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|  * Marek Szyprowski <m.szyprowski@samsung.com>
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|  * Lukasz Majewski <l.majewski@samsumg.com>
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|  *
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|  * SPDX-License-Identifier:	GPL-2.0+
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|  */
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| 
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| #include <common.h>
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| #include <asm/errno.h>
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| #include <linux/list.h>
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| #include <malloc.h>
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| 
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| #include <linux/usb/ch9.h>
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| #include <linux/usb/gadget.h>
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| 
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| #include <asm/byteorder.h>
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| #include <asm/unaligned.h>
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| #include <asm/io.h>
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| 
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| #include <asm/mach-types.h>
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| 
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| #include "dwc2_udc_otg_regs.h"
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| #include "dwc2_udc_otg_priv.h"
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| #include <usb/lin_gadget_compat.h>
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| 
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| #include <usb/dwc2_udc.h>
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| 
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| void otg_phy_init(struct dwc2_udc *dev)
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| {
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| 	unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
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| 	struct dwc2_usbotg_phy *phy =
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| 		(struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
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| 
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| 	dev->pdata->phy_control(1);
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| 
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| 	/* USB PHY0 Enable */
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| 	printf("USB PHY0 Enable\n");
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| 
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| 	/* Enable PHY */
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| 	writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
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| 
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| 	if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
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| 		writel((readl(&phy->phypwr)
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| 			&~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
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| 			&~FORCE_SUSPEND_0), &phy->phypwr);
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| 	else /* C110 GONI */
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| 		writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
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| 			&~FORCE_SUSPEND_0), &phy->phypwr);
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| 
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| 	if (s5p_cpu_id == 0x4412)
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| 		writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
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| 			EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
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| 		       &phy->phyclk); /* PLL 24Mhz */
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| 	else
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| 		writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
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| 		       CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
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| 
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| 	writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
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| 	       | PHY_SW_RST0, &phy->rstcon);
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| 	udelay(10);
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| 	writel(readl(&phy->rstcon)
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| 	       &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
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| 	udelay(10);
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| }
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| 
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| void otg_phy_off(struct dwc2_udc *dev)
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| {
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| 	unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
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| 	struct dwc2_usbotg_phy *phy =
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| 		(struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
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| 
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| 	/* reset controller just in case */
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| 	writel(PHY_SW_RST0, &phy->rstcon);
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| 	udelay(20);
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| 	writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
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| 	udelay(20);
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| 
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| 	writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
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| 	       | FORCE_SUSPEND_0, &phy->phypwr);
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| 
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| 	writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
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| 
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| 	writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
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| 	      &phy->phyclk);
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| 
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| 	udelay(10000);
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| 
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| 	dev->pdata->phy_control(0);
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| }
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