357 lines
10 KiB
C
357 lines
10 KiB
C
/*
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* (C) Copyright 2003-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2010
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
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#define CONFIG_A4M072 1 /* ... on A4M072 board */
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#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_TEXT_BASE 0xFE000000
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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/* define to enable silent console */
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#define CONFIG_SILENT_CONSOLE
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#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#define CONFIG_PCI
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#if defined(CONFIG_PCI)
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#endif
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#define CONFIG_SYS_XLB_PIPELINING 1
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#undef CONFIG_EEPRO100
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/* USB */
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_OHCI_BE_CONTROLLER
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#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_DISPLAY
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
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#define CONFIG_SYS_LOWBOOT 1
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#define CONFIG_SYS_LOWBOOT32 1
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#endif
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/*
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* Autobooting
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*/
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#define CONFIG_SYS_AUTOLOAD "n"
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#undef CONFIG_BOOTARGS
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#define CONFIG_PREBOOT "run try_update"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bk=run add_mtd ; run add_consolespec ; bootm 200000\0" \
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"cf1=diskboot 200000 0:1\0" \
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"bootcmd_cf1=run bcf1\0" \
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"bcf=setenv bootargs root=/dev/hda3\0" \
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"bootcmd_nfs=run bnfs\0" \
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"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
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"panic=1\0" \
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"bootcmd_nor=cp.b ${kernel_addr} 200000 100000;" \
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"run norargs addip; run bk\0" \
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"bnfs=nfs 200000 ${rootpath}/boot/uImage;" \
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"run nfsargs addip ; run bk\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"try_update=usb start;sleep 2;usb start;sleep 1;" \
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"fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;" \
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"source 2F0000\0" \
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"env_addr=FE060000\0" \
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"kernel_addr=FE100000\0" \
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"rootfs_addr=FE200000\0" \
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"add_mtd=setenv bootargs ${bootargs} mtdparts=" \
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"phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0" \
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"bcf1=run cf1; run bcf; run addip; run bk\0" \
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"add_consolespec=setenv bootargs ${bootargs} " \
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"console=/dev/null quiet\0" \
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"addip=if test -n ${ethaddr};" \
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"then if test -n ${ipaddr};" \
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"then setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:"\
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"${netmask}:${hostname}:${netdev}:off;" \
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"fi;" \
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"else;" \
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"setenv bootargs ${bootargs} no_ethaddr;" \
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"fi\0" \
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"hostname=CPUP0\0" \
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"netdev=eth0\0" \
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"bootcmd=run bootcmd_nor\0" \
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""
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/*
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* IPB Bus clocking configuration.
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*/
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#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010010x */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_SYS_EEPROM_WREN 1
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#define CONFIG_SYS_EEPROM_WP GPIO_PSC2_4
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFE000000
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#define CONFIG_SYS_FLASH_SIZE 0x02000000
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#if !defined(CONFIG_SYS_LOWBOOT)
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#error "CONFIG_SYS_LOWBOOT not defined?"
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#else /* CONFIG_SYS_LOWBOOT */
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#if defined(CONFIG_SYS_LOWBOOT32)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
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#endif
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#endif /* CONFIG_SYS_LOWBOOT */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS0_START}
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#define CONFIG_SYS_FLASH_BANKS_SIZES {CONFIG_SYS_CS0_SIZE}
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xF0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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/* Use SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_MPC5xxx_FEC_MII100
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/*
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* Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
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*/
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/* #define CONFIG_MPC5xxx_FEC_MII10 */
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#define CONFIG_PHY_ADDR 0x1f
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#define CONFIG_PHY_TYPE 0x79c874 /* AMD Phy Controller */
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/*
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* GPIO configuration
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x18000004
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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/* Flash at CSBoot, CS0 */
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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/* External SRAM at CS1 */
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#define CONFIG_SYS_CS1_START 0x62000000
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#define CONFIG_SYS_CS1_SIZE 0x00400000
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#define CONFIG_SYS_CS1_CFG 0x00009930
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#define CONFIG_SYS_SRAM_BASE CONFIG_SYS_CS1_START
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#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE
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/* LED display at CS7 */
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#define CONFIG_SYS_CS7_START 0x6a000000
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#define CONFIG_SYS_CS7_SIZE (64*1024)
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#define CONFIG_SYS_CS7_CFG 0x0000bf30
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x33333003
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#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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/*-----------------------------------------------------------------------
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* USB stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00001000 /* 0x4000 for SE mode */
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#define CONFIG_IDE_PREINIT
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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#define CONFIG_SYS_ATA_STRIDE 4
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#define CONFIG_ATAPI 1
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/*-----------------------------------------------------------------------
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* Open firmware flat tree support
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*-----------------------------------------------------------------------
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*/
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#define OF_CPU "PowerPC,5200@0"
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#define OF_SOC "soc5200@f0000000"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
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/* Support for the 7-segment display */
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#define CONFIG_SYS_DISP_CHR_RAM CONFIG_SYS_CS7_START
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#define CONFIG_SHOW_ACTIVITY /* used for display realization */
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#define CONFIG_SHOW_BOOT_PROGRESS
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#endif /* __CONFIG_H */
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