365 lines
11 KiB
C
365 lines
11 KiB
C
/*
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* (C) Copyright 2006
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* MicroSys GmbH
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*
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* (C) Copyright 2009
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* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC5200
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#define CONFIG_MPX5200 1 /* MPX5200 board */
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#define CONFIG_MPC5200_DDR 1 /* use DDR RAM */
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#define CONFIG_IPEK01 /* Motherboard is ipek01 */
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_TEXT_BASE 0xfc000000
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
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#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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/*
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* Video configuration for LIME GDC
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*/
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#define CONFIG_VIDEO
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#ifdef CONFIG_VIDEO
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#define CONFIG_VIDEO_MB862xx
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#define CONFIG_VIDEO_MB862xx_ACCEL
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#define VIDEO_FB_16BPP_WORD_SWAP
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_VIDEO_BMP_GZIP
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
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/* Lime clock frequency */
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#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
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/* SDRAM parameter */
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#define CONFIG_SYS_MB862xx_MMR 0x41c767e3
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#endif
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/*
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* PCI Mapping:
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* 0x40000000 - 0x4fffffff - PCI Memory
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* 0x50000000 - 0x50ffffff - PCI IO Space
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*/
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x10000000
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#define CONFIG_PCI_IO_BUS 0x50000000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x01000000
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#define CONFIG_MII 1
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#define CONFIG_EEPRO100 1
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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/* Partitions */
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#define CONFIG_DOS_PARTITION
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/* USB */
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_OHCI_BE_CONTROLLER
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
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/*
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* Command line configuration.
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*/
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP /* BMP support */
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#endif
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#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
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#define CONFIG_CMD_IDE /* IDE harddisk support */
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#define CONFIG_CMD_IRQ /* irqinfo */
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#define CONFIG_CMD_PCI /* pciinfo */
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#define CONFIG_SYS_LOWBOOT 1
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/*
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* Autobooting
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*/
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyPSC0\0" \
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"hostname=ipek01\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} " \
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"console=${consoledev},${baudrate}\0" \
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr} - ${fdtaddr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
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"net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
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"run nfsargs addip addtty;" \
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"bootm ${loadaddr} - ${fdtaddr}\0" \
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"rootpath=/opt/eldk/ppc_6xx\0" \
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"bootfile=ipek01/uImage\0" \
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"load=tftp 100000 ipek01/u-boot.bin\0" \
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"update=protect off FC000000 +60000; era FC000000 +60000; " \
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"cp.b 100000 FC000000 ${filesize}\0" \
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"upd=run load;run update\0" \
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"fdtaddr=800000\0" \
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"loadaddr=400000\0" \
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"fdtfile=ipek01/ipek01.dtb\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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/*
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* IPB Bus clocking configuration.
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*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
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/* PCI clock must be 33, because board will not boot */
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#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
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/*
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* Open firmware flat tree support
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*/
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#define OF_CPU "PowerPC,5200@0"
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#define OF_SOC "soc5200@f0000000"
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#define OF_TBCLK (bd->bi_busfreq / 4)
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/*
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* RTC configuration
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*/
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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#define CONFIG_SYS_FLASH_BASE 0xFC000000
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#define CONFIG_SYS_FLASH_SIZE 0x01000000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
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#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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/* use CFI flash driver */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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/*
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* Memory map
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*/
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#define CONFIG_SYS_MBAR 0xf0000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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#define CONFIG_SYS_SRAM_BASE 0xF1000000
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#define CONFIG_SYS_SRAM_SIZE 0x00200000
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#define CONFIG_SYS_LIME_BASE 0xE4000000
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#define CONFIG_SYS_LIME_SIZE 0x04000000
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#define CONFIG_SYS_FPGA_BASE 0xC0000000
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#define CONFIG_SYS_FPGA_SIZE 0x10000000
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#define CONFIG_SYS_MPEG_BASE 0xe2000000
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#define CONFIG_SYS_MPEG_SIZE 0x01000000
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#define CONFIG_SYS_CF_BASE 0xe1000000
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#define CONFIG_SYS_CF_SIZE 0x01000000
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/* Use SRAM until RAM will be available */
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#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
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/* End of used area in DPRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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# define CONFIG_SYS_RAMBOOT 1
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#endif
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#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC5xxx_FEC 1
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#define CONFIG_MPC5xxx_FEC_MII100
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#define CONFIG_PHY_ADDR 0x00
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/*
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* GPIO configuration
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*/
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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/*
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* Various low-level settings
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*/
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#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
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#define CONFIG_SYS_HID0_FINAL HID0_ICE
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#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
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#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
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#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
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#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
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#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
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#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
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#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
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#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
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#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
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#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
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#ifdef CONFIG_SYS_PCISPEED_66
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#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
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#define CONFIG_SYS_CS1_CFG 0x0004FB00
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#define CONFIG_SYS_CS2_CFG 0x0006F900
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#else
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#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
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#define CONFIG_SYS_CS1_CFG 0x0001FB00
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#define CONFIG_SYS_CS2_CFG 0x0002F90C
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#endif
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/*
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* Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
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* waitstates, writeswap and readswap enabled
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*/
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#define CONFIG_SYS_CS3_CFG 0x00FFFB0C
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#define CONFIG_SYS_CS6_CFG 0x00FFFB0C
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#define CONFIG_SYS_CS7_CFG 0x4040751C
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x33330000
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#define CONFIG_SYS_RESET_ADDRESS 0xff000000
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/*-----------------------------------------------------------------------
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* USB stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_USB_CLOCK 0x0001BBBB
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#define CONFIG_USB_CONFIG 0x00005000
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff Supports IDE harddisk
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_PREINIT
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
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/* Offset for data I/O */
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#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
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/* Interval between registers */
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#define CONFIG_SYS_ATA_STRIDE 4
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#endif /* __CONFIG_H */
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