72 lines
2.3 KiB
C
72 lines
2.3 KiB
C
/*
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* Configuation settings for MPR2
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*
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* Copyright (C) 2008
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* Mark Jonas <mark.jonas@de.bosch.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MPR2_H
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#define __MPR2_H
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/* Supported commands */
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/* Default environment variables */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS "console=ttySC0,115200"
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#define CONFIG_BOOTFILE "/boot/zImage"
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#define CONFIG_LOADADDR 0x8E000000
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#define CONFIG_VERSION_VARIABLE
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/* CPU and platform */
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#define CONFIG_CPU_SH7720 1
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#define CONFIG_MPR2 1
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/* U-Boot internals */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
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#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
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#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
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#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
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/* Memory */
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#define CONFIG_SYS_SDRAM_BASE 0x8C000000
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
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/* Flash */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BASE 0xA0000000
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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/* Clocks */
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#define CONFIG_SYS_CLK_FREQ 24000000
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
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/* UART */
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#define CONFIG_SCIF_CONSOLE 1
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#define CONFIG_CONS_SCIF0 1
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#endif /* __MPR2_H */
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