100 lines
3.0 KiB
C
100 lines
3.0 KiB
C
/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_SOCFPGA_SR1500_H__
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#define __CONFIG_SOCFPGA_SR1500_H__
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#include <asm/arch/base_addr_ac5.h>
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_DOS_PARTITION
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#define CONFIG_FAT_WRITE
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#define CONFIG_HW_WATCHDOG
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/* Memory configurations */
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#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
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/* Booting Linux */
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
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#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
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#define CONFIG_LOADADDR 0x01000000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
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/* Ethernet on SoC (EMAC) */
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#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
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/* The PHY is autodetected, so no MII PHY address is needed here */
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#define CONFIG_PHY_MARVELL
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#define PHY_ANEG_TIMEOUT 8000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"verify=n\0" \
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"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
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"bootm ${loadaddr} - ${fdt_addr}\0" \
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"bootimage=zImage\0" \
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"fdt_addr=100\0" \
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"fdtimage=socfpga.dtb\0" \
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"fsloadcmd=ext2load\0" \
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"bootm ${loadaddr} - ${fdt_addr}\0" \
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"mmcroot=/dev/mmcblk0p2\0" \
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"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
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" root=${mmcroot} rw rootwait;" \
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"bootz ${loadaddr} - ${fdt_addr}\0" \
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"mmcload=mmc rescan;" \
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"load mmc 0:1 ${loadaddr} ${bootimage};" \
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"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
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"qspiload=sf probe && mtdparts default && run ubiload\0" \
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"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
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" ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
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"bootz ${loadaddr} - ${fdt_addr}\0" \
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"ubiload=ubi part UBI && ubifsmount ubi0 && " \
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"ubifsload ${loadaddr} /boot/${bootimage} && " \
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"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
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/* Environment */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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/* Enable SPI NOR flash reset, needed for SPI booting */
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#define CONFIG_SPI_N25Q256A_RESET
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/*
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* Bootcounter
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*/
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#define CONFIG_BOOTCOUNT_LIMIT
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/* last 2 lwords in OCRAM */
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#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
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#define CONFIG_SYS_BOOTCOUNT_BE
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/* Environment setting for SPI flash */
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_SIZE (16 * 1024)
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#define CONFIG_ENV_OFFSET 0x000e0000
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MODE SPI_MODE_3
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#define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
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#define CONFIG_SF_DEFAULT_SPEED 100000000
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/*
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* The QSPI NOR flash layout on SR1500:
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*
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* 0000.0000 - 0003.ffff: SPL (4 times)
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* 0004.0000 - 000d.ffff: U-Boot
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* 000e.0000 - 000e.ffff: env1
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* 000f.0000 - 000f.ffff: env2
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*/
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/* The rest of the configuration is shared */
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#include <configs/socfpga_common.h>
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#endif /* __CONFIG_SOCFPGA_SR1500_H__ */
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