194 lines
5.4 KiB
ArmAsm
194 lines
5.4 KiB
ArmAsm
/*
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* armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
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*
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* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
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*
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <version.h>
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#include <asm/system.h>
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#include <linux/linkage.h>
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/*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************/
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.globl reset
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reset:
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bl save_boot_params
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/*
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* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
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* except if in HYP mode already
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*/
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mrs r0, cpsr
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and r1, r0, #0x1f @ mask mode bits
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teq r1, #0x1a @ test for HYP mode
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bicne r0, r0, #0x1f @ clear all mode bits
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orrne r0, r0, #0x13 @ set SVC mode
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orr r0, r0, #0xc0 @ disable FIQ and IRQ
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msr cpsr,r0
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/*
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* Setup vector:
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* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
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* Continue to use ROM code vector only in OMAP4 spl)
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*/
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#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
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/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
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mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
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bic r0, #CR_V @ V = 0
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mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
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/* Set vector address in CP15 VBAR register */
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ldr r0, =_start
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mcr p15, 0, r0, c12, c0, 0 @Set VBAR
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#endif
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/* the mask ROM code should have PLL and others stable */
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_cp15
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bl cpu_init_crit
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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ENTRY(c_runtime_cpu_setup)
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/*
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* If I-cache is enabled invalidate it
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*/
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#ifndef CONFIG_SYS_ICACHE_OFF
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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#endif
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/*
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* Move vector table
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*/
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/* Set vector address in CP15 VBAR register */
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ldr r0, =_start
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mcr p15, 0, r0, c12, c0, 0 @Set VBAR
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bx lr
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ENDPROC(c_runtime_cpu_setup)
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/*************************************************************************
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*
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* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
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* __attribute__((weak));
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*
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* Stack pointer is not yet initialized at this moment
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* Don't save anything to stack even if compiled with -O0
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*
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*************************************************************************/
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ENTRY(save_boot_params)
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bx lr @ back to my caller
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ENDPROC(save_boot_params)
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.weak save_boot_params
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/*************************************************************************
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*
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* cpu_init_cp15
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*
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* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
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* CONFIG_SYS_ICACHE_OFF is defined.
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*
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*************************************************************************/
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ENTRY(cpu_init_cp15)
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/*
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* Invalidate L1 I/D
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*/
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mov r0, #0 @ set up for MCR
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
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bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
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orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
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orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
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#ifdef CONFIG_SYS_ICACHE_OFF
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bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
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#else
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
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#endif
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mcr p15, 0, r0, c1, c0, 0
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#ifdef CONFIG_ARM_ERRATA_716044
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mrc p15, 0, r0, c1, c0, 0 @ read system control register
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orr r0, r0, #1 << 11 @ set bit #11
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mcr p15, 0, r0, c1, c0, 0 @ write system control register
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#endif
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#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 4 @ set bit #4
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 6 @ set bit #6
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_751472
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 11 @ set bit #11
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_761320
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 21 @ set bit #21
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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mov pc, lr @ back to my caller
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ENDPROC(cpu_init_cp15)
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************/
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ENTRY(cpu_init_crit)
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/*
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* Jump to board specific initialization...
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* The Mask ROM will have already initialized
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* basic memory. Go here to bump up clock rate and handle
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* wake up conditions.
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*/
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b lowlevel_init @ go setup pll,mux,memory
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ENDPROC(cpu_init_crit)
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#endif
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