437 lines
12 KiB
C
437 lines
12 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/armv8/mmu.h>
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#include <asm/io.h>
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#include <asm/arch-fsl-lsch3/immap_lsch3.h>
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#include "cpu.h"
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#include "speed.h"
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#include <fsl_mc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_DCACHE_OFF
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/*
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* To start MMU before DDR is available, we create MMU table in SRAM.
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* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
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* levels of translation tables here to cover 40-bit address space.
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* We use 4KB granule size, with 40 bits physical address, T0SZ=24
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* Level 0 IA[39], table address @0
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* Level 1 IA[31:30], table address @01000, 0x2000
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* Level 2 IA[29:21], table address @0x3000
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*/
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#define SECTION_SHIFT_L0 39UL
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#define SECTION_SHIFT_L1 30UL
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#define SECTION_SHIFT_L2 21UL
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#define BLOCK_SIZE_L0 0x8000000000UL
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#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
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#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
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#define CONFIG_SYS_IFC_BASE 0x30000000
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#define CONFIG_SYS_IFC_SIZE 0x10000000
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#define CONFIG_SYS_IFC_BASE2 0x500000000
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#define CONFIG_SYS_IFC_SIZE2 0x100000000
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#define TCR_EL2_PS_40BIT (2 << 16)
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#define LSCH3_VA_BITS (40)
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#define LSCH3_TCR (TCR_TG0_4K | \
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TCR_EL2_PS_40BIT | \
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TCR_SHARED_NON | \
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TCR_ORGN_NC | \
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TCR_IRGN_NC | \
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TCR_T0SZ(LSCH3_VA_BITS))
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/*
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* Final MMU
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* Let's start from the same layout as early MMU and modify as needed.
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* IFC regions will be cache-inhibit.
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*/
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#define FINAL_QBMAN_CACHED_MEM 0x818000000UL
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#define FINAL_QBMAN_CACHED_SIZE 0x4000000
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static inline void early_mmu_setup(void)
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{
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int el;
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u64 i;
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u64 section_l1t0, section_l1t1, section_l2;
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u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
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u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
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u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
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u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
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level0_table[0] =
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(u64)level1_table_0 | PMD_TYPE_TABLE;
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level0_table[1] =
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(u64)level1_table_1 | PMD_TYPE_TABLE;
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/*
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* set level 1 table 0 to cache_inhibit, covering 0 to 512GB
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* set level 1 table 1 to cache enabled, covering 512GB to 1TB
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* set level 2 table to cache-inhibit, covering 0 to 1GB
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*/
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section_l1t0 = 0;
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section_l1t1 = BLOCK_SIZE_L0;
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section_l2 = 0;
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for (i = 0; i < 512; i++) {
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set_pgtable_section(level1_table_0, i, section_l1t0,
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MT_DEVICE_NGNRNE);
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set_pgtable_section(level1_table_1, i, section_l1t1,
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MT_NORMAL);
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set_pgtable_section(level2_table, i, section_l2,
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MT_DEVICE_NGNRNE);
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section_l1t0 += BLOCK_SIZE_L1;
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section_l1t1 += BLOCK_SIZE_L1;
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section_l2 += BLOCK_SIZE_L2;
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}
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level1_table_0[0] =
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(u64)level2_table | PMD_TYPE_TABLE;
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level1_table_0[1] =
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0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT |
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PMD_ATTRINDX(MT_DEVICE_NGNRNE);
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level1_table_0[2] =
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0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
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PMD_ATTRINDX(MT_NORMAL);
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level1_table_0[3] =
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0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
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PMD_ATTRINDX(MT_NORMAL);
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/* Rewrite table to enable cache */
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set_pgtable_section(level2_table,
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CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
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CONFIG_SYS_FSL_OCRAM_BASE,
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MT_NORMAL);
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for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2;
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i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE)
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>> SECTION_SHIFT_L2; i++) {
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section_l2 = i << SECTION_SHIFT_L2;
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set_pgtable_section(level2_table, i,
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section_l2, MT_NORMAL);
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}
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el = current_el();
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set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES);
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set_sctlr(get_sctlr() | CR_M);
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}
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/*
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* This final tale looks similar to early table, but different in detail.
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* These tables are in regular memory. Cache on IFC is disabled. One sub table
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* is added to enable cache for QBMan.
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*/
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static inline void final_mmu_setup(void)
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{
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int el;
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u64 i, tbl_base, tbl_limit, section_base;
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u64 section_l1t0, section_l1t1, section_l2;
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u64 *level0_table = (u64 *)gd->arch.tlb_addr;
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u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
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u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
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u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
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u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
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level0_table[0] =
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(u64)level1_table_0 | PMD_TYPE_TABLE;
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level0_table[1] =
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(u64)level1_table_1 | PMD_TYPE_TABLE;
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/*
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* set level 1 table 0 to cache_inhibit, covering 0 to 512GB
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* set level 1 table 1 to cache enabled, covering 512GB to 1TB
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* set level 2 table 0 to cache-inhibit, covering 0 to 1GB
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*/
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section_l1t0 = 0;
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section_l1t1 = BLOCK_SIZE_L0;
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section_l2 = 0;
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for (i = 0; i < 512; i++) {
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set_pgtable_section(level1_table_0, i, section_l1t0,
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MT_DEVICE_NGNRNE);
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set_pgtable_section(level1_table_1, i, section_l1t1,
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MT_NORMAL);
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set_pgtable_section(level2_table_0, i, section_l2,
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MT_DEVICE_NGNRNE);
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section_l1t0 += BLOCK_SIZE_L1;
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section_l1t1 += BLOCK_SIZE_L1;
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section_l2 += BLOCK_SIZE_L2;
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}
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level1_table_0[0] =
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(u64)level2_table_0 | PMD_TYPE_TABLE;
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level1_table_0[2] =
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0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
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PMD_ATTRINDX(MT_NORMAL);
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level1_table_0[3] =
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0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
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PMD_ATTRINDX(MT_NORMAL);
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/* Rewrite table to enable cache */
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set_pgtable_section(level2_table_0,
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CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
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CONFIG_SYS_FSL_OCRAM_BASE,
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MT_NORMAL);
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/*
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* Fill in other part of tables if cache is needed
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* If finer granularity than 1GB is needed, sub table
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* should be created.
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*/
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section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1);
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i = section_base >> SECTION_SHIFT_L1;
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level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE;
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section_l2 = section_base;
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for (i = 0; i < 512; i++) {
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set_pgtable_section(level2_table_1, i, section_l2,
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MT_DEVICE_NGNRNE);
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section_l2 += BLOCK_SIZE_L2;
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}
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tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1);
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tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) &
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(BLOCK_SIZE_L1 - 1);
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for (i = tbl_base >> SECTION_SHIFT_L2;
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i < tbl_limit >> SECTION_SHIFT_L2; i++) {
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section_l2 = section_base + (i << SECTION_SHIFT_L2);
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set_pgtable_section(level2_table_1, i,
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section_l2, MT_NORMAL);
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}
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/* flush new MMU table */
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flush_dcache_range(gd->arch.tlb_addr,
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gd->arch.tlb_addr + gd->arch.tlb_size);
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/* point TTBR to the new table */
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el = current_el();
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asm volatile("dsb sy");
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if (el == 1) {
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asm volatile("msr ttbr0_el1, %0"
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: : "r" ((u64)level0_table) : "memory");
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} else if (el == 2) {
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asm volatile("msr ttbr0_el2, %0"
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: : "r" ((u64)level0_table) : "memory");
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} else if (el == 3) {
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asm volatile("msr ttbr0_el3, %0"
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: : "r" ((u64)level0_table) : "memory");
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} else {
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hang();
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}
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asm volatile("isb");
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/*
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* MMU is already enabled, just need to invalidate TLB to load the
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* new table. The new table is compatible with the current table, if
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* MMU somehow walks through the new table before invalidation TLB,
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* it still works. So we don't need to turn off MMU here.
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*/
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}
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int arch_cpu_init(void)
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{
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icache_enable();
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__asm_invalidate_dcache_all();
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__asm_invalidate_tlb_all();
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early_mmu_setup();
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set_sctlr(get_sctlr() | CR_C);
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return 0;
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}
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/*
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* flush_l3_cache
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* Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power
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* state, by writing to HP-F P-state request register.
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* Fixme: This function should moved to a common file if other SoCs also use
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* the same Dickens.
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*/
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#define HNF0_PSTATE_REQ 0x04200010
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#define HNF1_PSTATE_REQ 0x04210010
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#define HNF2_PSTATE_REQ 0x04220010
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#define HNF3_PSTATE_REQ 0x04230010
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#define HNF4_PSTATE_REQ 0x04240010
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#define HNF5_PSTATE_REQ 0x04250010
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#define HNF6_PSTATE_REQ 0x04260010
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#define HNF7_PSTATE_REQ 0x04270010
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#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC)
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#define HNFPSTAT_FAM 0x3
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#define HNFPSTAT_SFONLY 0x01
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static void hnf_pstate_req(u64 *ptr, u64 state)
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{
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int timeout = 1000;
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out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3));
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ptr++;
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/* checking if the transition is completed */
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while (timeout > 0) {
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if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3))
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break;
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udelay(100);
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timeout--;
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}
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}
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void flush_l3_cache(void)
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{
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hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY);
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hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY);
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hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY);
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hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY);
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hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY);
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hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY);
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hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY);
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hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY);
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hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM);
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hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM);
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hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM);
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hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM);
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hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM);
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hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM);
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hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM);
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hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM);
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}
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/*
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* This function is called from lib/board.c.
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* It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
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* There is no need to disable d-cache for this operation.
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*/
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void enable_caches(void)
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{
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final_mmu_setup();
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__asm_invalidate_tlb_all();
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}
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#endif
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static inline u32 initiator_type(u32 cluster, int init_id)
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{
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
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u32 type = in_le32(&gur->tp_ityp[idx]);
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if (type & TP_ITYP_AV)
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return type;
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return 0;
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}
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u32 cpu_mask(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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int i = 0, count = 0;
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u32 cluster, type, mask = 0;
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do {
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int j;
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cluster = in_le32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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type = initiator_type(cluster, j);
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if (type) {
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if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
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mask |= 1 << count;
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count++;
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}
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
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return mask;
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}
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/*
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* Return the number of cores on this SOC.
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*/
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int cpu_numcores(void)
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{
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return hweight32(cpu_mask());
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}
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int fsl_qoriq_core_to_cluster(unsigned int core)
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{
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struct ccsr_gur __iomem *gur =
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(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
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int i = 0, count = 0;
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u32 cluster;
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do {
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int j;
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cluster = in_le32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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if (initiator_type(cluster, j)) {
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if (count == core)
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return i;
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count++;
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}
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
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return -1; /* cannot identify the cluster */
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}
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u32 fsl_qoriq_core_to_type(unsigned int core)
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{
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struct ccsr_gur __iomem *gur =
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(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
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int i = 0, count = 0;
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u32 cluster, type;
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do {
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int j;
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cluster = in_le32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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type = initiator_type(cluster, j);
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if (type) {
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if (count == core)
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return type;
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count++;
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}
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
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return -1; /* cannot identify the cluster */
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}
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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struct sys_info sysinfo;
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char buf[32];
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unsigned int i, core;
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u32 type;
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get_sys_info(&sysinfo);
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puts("Clock Configuration:");
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for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
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if (!(i % 3))
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puts("\n ");
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type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
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printf("CPU%d(%s):%-4s MHz ", core,
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type == TY_ITYP_VER_A7 ? "A7 " :
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(type == TY_ITYP_VER_A53 ? "A53" :
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(type == TY_ITYP_VER_A57 ? "A57" : " ")),
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strmhz(buf, sysinfo.freq_processor[core]));
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}
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printf("\n Bus: %-4s MHz ",
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strmhz(buf, sysinfo.freq_systembus));
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printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
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puts("\n");
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return 0;
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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int error = 0;
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#ifdef CONFIG_FSL_MC_ENET
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error = mc_init(bis);
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#endif
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return error;
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}
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