85 lines
1.5 KiB
C
85 lines
1.5 KiB
C
/*
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* K2E: Clock management APIs
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_K2E_H
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#define __ASM_ARCH_CLOCK_K2E_H
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enum ext_clk_e {
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sys_clk,
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alt_core_clk,
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pa_clk,
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ddr3_clk,
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mcm_clk,
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pcie_clk,
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sgmii_clk,
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xgmii_clk,
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usb_clk,
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ext_clk_count /* number of external clocks */
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};
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extern unsigned int external_clk[ext_clk_count];
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enum clk_e {
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core_pll_clk,
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pass_pll_clk,
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ddr3_pll_clk,
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sys_clk0_clk,
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sys_clk0_1_clk,
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sys_clk0_2_clk,
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sys_clk0_3_clk,
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sys_clk0_4_clk,
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sys_clk0_6_clk,
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sys_clk0_8_clk,
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sys_clk0_12_clk,
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sys_clk0_24_clk,
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sys_clk1_clk,
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sys_clk1_3_clk,
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sys_clk1_4_clk,
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sys_clk1_6_clk,
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sys_clk1_12_clk,
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sys_clk2_clk,
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sys_clk3_clk
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};
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#define KS2_CLK1_6 sys_clk0_6_clk
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/* PLL identifiers */
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enum pll_type_e {
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CORE_PLL,
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PASS_PLL,
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DDR3_PLL,
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};
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enum {
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SPD800,
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SPD850,
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SPD1000,
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SPD1250,
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SPD1350,
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SPD1400,
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SPD1500,
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SPD_RSV
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};
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#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
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#define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
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#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
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#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
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#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
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#define CORE_PLL_1250 {CORE_PLL, 25, 1, 2}
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#define CORE_PLL_1350 {CORE_PLL, 27, 1, 2}
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#define CORE_PLL_1400 {CORE_PLL, 28, 1, 2}
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#define CORE_PLL_1500 {CORE_PLL, 30, 1, 2}
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#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
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#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
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#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
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#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
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#endif
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