162 lines
3.2 KiB
C
162 lines
3.2 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/mipsregs.h>
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#include <asm/cacheops.h>
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#include <asm/reboot.h>
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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void __attribute__((weak)) _machine_restart(void)
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{
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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_machine_restart();
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fprintf(stderr, "*** reset failed ***\n");
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return 0;
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}
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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static inline unsigned long icache_line_size(void)
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{
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return CONFIG_SYS_CACHELINE_SIZE;
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}
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static inline unsigned long dcache_line_size(void)
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{
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return CONFIG_SYS_CACHELINE_SIZE;
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}
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#else /* !CONFIG_SYS_CACHELINE_SIZE */
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static inline unsigned long icache_line_size(void)
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{
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unsigned long conf1, il;
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conf1 = read_c0_config1();
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il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT;
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if (!il)
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return 0;
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return 2 << il;
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}
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static inline unsigned long dcache_line_size(void)
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{
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unsigned long conf1, dl;
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conf1 = read_c0_config1();
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dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT;
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if (!dl)
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return 0;
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return 2 << dl;
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}
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#endif /* !CONFIG_SYS_CACHELINE_SIZE */
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long ilsize = icache_line_size();
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unsigned long dlsize = dcache_line_size();
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unsigned long addr, aend;
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/* aend will be miscalculated when size is zero, so we return here */
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if (size == 0)
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return;
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addr = start_addr & ~(dlsize - 1);
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aend = (start_addr + size - 1) & ~(dlsize - 1);
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if (ilsize == dlsize) {
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/* flush I-cache & D-cache simultaneously */
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while (1) {
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cache_op(HIT_WRITEBACK_INV_D, addr);
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cache_op(HIT_INVALIDATE_I, addr);
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if (addr == aend)
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break;
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addr += dlsize;
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}
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return;
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}
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/* flush D-cache */
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while (1) {
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cache_op(HIT_WRITEBACK_INV_D, addr);
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if (addr == aend)
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break;
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addr += dlsize;
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}
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/* flush I-cache */
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addr = start_addr & ~(ilsize - 1);
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aend = (start_addr + size - 1) & ~(ilsize - 1);
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while (1) {
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cache_op(HIT_INVALIDATE_I, addr);
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if (addr == aend)
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break;
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addr += ilsize;
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}
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}
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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while (1) {
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cache_op(HIT_WRITEBACK_INV_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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while (1) {
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cache_op(HIT_INVALIDATE_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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}
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}
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void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
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{
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write_c0_entrylo0(low0);
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write_c0_pagemask(pagemask);
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write_c0_entrylo1(low1);
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write_c0_entryhi(hi);
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write_c0_index(index);
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tlb_write_indexed();
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}
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int cpu_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SOC_AU1X00
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au1x00_enet_initialize(bis);
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#endif
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return 0;
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}
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