73 lines
2.1 KiB
C
73 lines
2.1 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "common.h"
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#include "asm/errno.h"
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#include "asm/io.h"
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#include "asm/immap_85xx.h"
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#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
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#define NUM_OF_PINS 32
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void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
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{
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u32 pin_2bit_mask;
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u32 pin_2bit_dir;
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u32 pin_2bit_assign;
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u32 pin_1bit_mask;
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u32 tmp_val;
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile par_io_t *par_io = (volatile par_io_t *)
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&(gur->qe_par_io);
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/* Caculate pin location and 2bit mask and dir */
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pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
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pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
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/* Setup the direction */
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tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
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in_be32(&par_io[port].cpdir2) :
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in_be32(&par_io[port].cpdir1);
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if (pin > (NUM_OF_PINS/2) -1) {
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out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val);
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out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val);
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} else {
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out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val);
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out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val);
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}
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/* Calculate pin location for 1bit mask */
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pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
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/* Setup the open drain */
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tmp_val = in_be32(&par_io[port].cpodr);
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if (open_drain)
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out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val);
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else
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out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val);
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/* Setup the assignment */
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tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
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in_be32(&par_io[port].cppar2):
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in_be32(&par_io[port].cppar1);
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pin_2bit_assign = (u32)(assign
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<< (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
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/* Clear and set 2 bits mask */
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if (pin > (NUM_OF_PINS/2) - 1) {
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out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val);
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out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val);
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} else {
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out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val);
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out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val);
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}
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}
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#endif /* CONFIG_QE */
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