446 lines
12 KiB
C
446 lines
12 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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typedef unsigned short FLASH_PORT_WIDTH;
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typedef volatile unsigned short FLASH_PORT_WIDTHV;
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#define FLASH_ID_MASK 0x00FF
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define FLASH_CYCLE1 0x0555
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#define FLASH_CYCLE2 0x0aaa
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#define FLASH_ID1 0x00
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#define FLASH_ID2 0x01
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#define FLASH_ID3 0x0E
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#define FLASH_ID4 0x0F
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size(FPWV * addr, flash_info_t * info);
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static void flash_reset(flash_info_t * info);
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static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
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static flash_info_t *flash_get_info(ulong base);
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/*-----------------------------------------------------------------------
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* flash_init()
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*
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* sets up flash_info and returns size of FLASH (bytes)
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*/
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unsigned long flash_init(void)
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{
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unsigned long size = 0;
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int i = 0;
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extern void flash_preinit(void);
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extern void flash_afterinit(uint, ulong, ulong);
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ulong flashbase = CONFIG_SYS_FLASH_BASE;
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flash_preinit();
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/* There is only ONE FLASH device */
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memset(&flash_info[i], 0, sizeof(flash_info_t));
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flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
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size += flash_info[i].size;
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
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flash_get_info(CONFIG_SYS_MONITOR_BASE));
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#endif
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#ifdef CONFIG_ENV_IS_IN_FLASH
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/* ENV protection ON by default */
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flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
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flash_get_info(CONFIG_ENV_ADDR));
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#endif
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flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
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return size ? size : 1;
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_reset(flash_info_t * info) {
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FPWV *base = (FPWV *) (info->start[0]);
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/* Put FLASH back in read mode */
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
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*base = (FPW) 0x00FF00FF; /* Intel Read Mode */
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} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) {
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*base = (FPW) 0x00F000F0; /* AMD Read Mode */
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}
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}
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/*-----------------------------------------------------------------------
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*/
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static flash_info_t *flash_get_info(ulong base) {
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int i;
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flash_info_t *info;
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
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info = &flash_info[i];
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if ((info->size) && (info->start[0] <= base)
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&& (base <= info->start[0] + info->size - 1)) {
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break;
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}
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}
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return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info(flash_info_t * info) {
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int i;
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char *fmt;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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printf("AMD ");
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break;
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default:
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printf("Unknown Vendor ");
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break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AMLV256U:
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fmt = "29LV256M (256 Mbit)\n";
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break;
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default:
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fmt = "Unknown Chip Type\n";
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break;
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}
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printf(fmt);
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printf(" Size: %ld MB in %d Sectors\n", info->size >> 20,
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info->sector_count);
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printf(" Sector Start Addresses:");
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for (i = 0; i < info->sector_count; ++i) {
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ulong size;
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int erased;
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ulong *flash = (unsigned long *)info->start[i];
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if ((i % 5) == 0) {
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printf("\n ");
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}
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/*
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* Check if whole sector is erased
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*/
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size =
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(i !=
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(info->sector_count - 1)) ? (info->start[i + 1] -
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info->start[i]) >> 2 : (info->
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start
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[0] +
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info->
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size -
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info->
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start
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[i])
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>> 2;
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for (flash = (unsigned long *)info->start[i], erased = 1;
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(flash != (unsigned long *)info->start[i] + size)
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&& erased; flash++) {
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erased = *flash == ~0x0UL;
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}
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printf(" %08lX %s %s", info->start[i], erased ? "E" : " ",
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info->protect[i] ? "(RO)" : " ");
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}
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printf("\n");
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}
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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ulong flash_get_size(FPWV * addr, flash_info_t * info) {
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int i;
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/* Write auto select command: read Manufacturer ID */
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/* Write auto select command sequence and test FLASH answer */
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addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
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addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
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addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */
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/* The manufacturer codes are only 1 byte, so just use 1 byte. */
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/* This works for any bus width and any FLASH device width. */
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udelay(100);
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switch (addr[FLASH_ID1] & 0x00ff) {
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case (uchar) AMD_MANUFACT:
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info->flash_id = FLASH_MAN_AMD;
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break;
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default:
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printf("unknown vendor=%x ", addr[FLASH_ID1] & 0xff);
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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break;
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}
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/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
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if (info->flash_id != FLASH_UNKNOWN) {
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switch ((FPW) addr[FLASH_ID2]) {
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case (FPW) AMD_ID_MIRROR:
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/* MIRROR BIT FLASH, read more ID bytes */
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if ((FPW) addr[FLASH_ID3] == (FPW) AMD_ID_LV256U_2
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&& (FPW) addr[FLASH_ID4] == (FPW) AMD_ID_LV256U_3) {
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/* attention: only the first 16 MB will be used in u-boot */
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info->flash_id += FLASH_AMLV256U;
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info->sector_count = 512;
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info->size = 0x02000000;
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for (i = 0; i < info->sector_count; i++) {
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info->start[i] =
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(ulong) addr + 0x10000 * i;
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}
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break;
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}
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/* fall thru to here ! */
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default:
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printf("unknown AMD device=%x %x %x",
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(FPW) addr[FLASH_ID2], (FPW) addr[FLASH_ID3],
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(FPW) addr[FLASH_ID4]);
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0x800000;
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break;
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}
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/* Put FLASH back in read mode */
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flash_reset(info);
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}
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return (info->size);
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase(flash_info_t * info, int s_first, int s_last) {
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FPWV *addr;
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int flag, prot, sect;
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int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
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ulong start, now, last;
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int rcode = 0;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf("- missing\n");
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} else {
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printf("- no sectors to erase\n");
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}
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return 1;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AMLV256U:
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break;
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case FLASH_UNKNOWN:
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default:
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printf("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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prot = 0;
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for (sect = s_first; sect <= s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf("\n");
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}
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last = get_timer(0);
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
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if (info->protect[sect] != 0) { /* protected, skip it */
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continue;
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}
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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addr = (FPWV *) (info->start[sect]);
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if (intel) {
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*addr = (FPW) 0x00500050; /* clear status register */
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*addr = (FPW) 0x00200020; /* erase setup */
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*addr = (FPW) 0x00D000D0; /* erase confirm */
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} else {
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/* must be AMD style if not Intel */
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FPWV *base; /* first address in bank */
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base = (FPWV *) (info->start[0]);
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base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
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base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
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base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */
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base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
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base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
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*addr = (FPW) 0x00300030; /* erase sector */
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}
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/* re-enable interrupts if necessary */
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if (flag) {
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enable_interrupts();
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}
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start = get_timer(0);
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/* wait at least 50us for AMD, 80us for Intel. */
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/* Let's wait 1 ms. */
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udelay(1000);
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while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
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if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
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printf("Timeout\n");
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if (intel) {
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/* suspend erase */
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*addr = (FPW) 0x00B000B0;
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}
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flash_reset(info); /* reset to read mode */
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rcode = 1; /* failed */
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break;
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}
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/* show that we're waiting */
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if ((get_timer(last)) > CONFIG_SYS_HZ) {
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/* every second */
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putc('.');
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last = get_timer(0);
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}
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}
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/* show that we're waiting */
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if ((get_timer(last)) > CONFIG_SYS_HZ) {
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/* every second */
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putc('.');
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last = get_timer(0);
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}
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flash_reset(info); /* reset to read mode */
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}
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printf(" done\n");
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return (rcode);
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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{
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FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
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int bytes; /* number of bytes to program in current word */
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int left; /* number of bytes left to program */
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int i, res;
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for (left = cnt, res = 0;
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left > 0 && res == 0;
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addr += sizeof(data), left -= sizeof(data) - bytes) {
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bytes = addr & (sizeof(data) - 1);
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addr &= ~(sizeof(data) - 1);
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/* combine source and destination data so can program
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* an entire word of 16 or 32 bits
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*/
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for (i = 0; i < sizeof(data); i++) {
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data <<= 8;
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if (i < bytes || i - bytes >= left)
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data += *((uchar *) addr + i);
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else
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data += *src++;
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}
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/* write one word to the flash */
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD:
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res = write_word_amd(info, (FPWV *) addr, data);
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break;
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default:
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/* unknown flash type, error! */
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printf("missing or unknown FLASH type\n");
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res = 1; /* not really a timeout, but gives error */
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break;
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}
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}
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return (res);
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}
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/*-----------------------------------------------------------------------
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* Write a word to Flash for AMD FLASH
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* A word is 16 or 32 bits, whichever the bus width of the flash bank
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* (not an individual chip) is.
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*
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* returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
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ulong start;
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int flag;
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int res = 0; /* result, assume success */
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FPWV *base; /* first address in flash bank */
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/* Check if Flash is (sufficiently) erased */
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if ((*dest & data) != data) {
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return (2);
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}
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base = (FPWV *) (info->start[0]);
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */
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base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */
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base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */
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*dest = data; /* start programming the data */
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/* re-enable interrupts if necessary */
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if (flag) {
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enable_interrupts();
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}
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start = get_timer(0);
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/* data polling for D7 */
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while (res == 0
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&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
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if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
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*dest = (FPW) 0x00F000F0; /* reset bank */
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res = 1;
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}
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}
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return (res);
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}
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