168 lines
3.9 KiB
C
168 lines
3.9 KiB
C
/* Copyright (C) 2011
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* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* This is a basic implementation of the SDMA/DMA4 controller of OMAP3
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* Tested on Silicon Revision major:0x4 minor:0x0
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/omap3.h>
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#include <asm/arch/dma.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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static struct dma4 *dma4_cfg = (struct dma4 *)OMAP34XX_DMA4_BASE;
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uint32_t dma_active; /* if a transfer is started the respective
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bit is set for the logical channel */
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/* Check if we have the given channel
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* PARAMETERS:
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* chan: Channel number
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*
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* RETURN of non-zero means error */
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static inline int check_channel(uint32_t chan)
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{
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if (chan < CHAN_NR_MIN || chan > CHAN_NR_MAX)
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return -EINVAL;
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return 0;
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}
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static inline void reset_irq(uint32_t chan)
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{
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/* reset IRQ reason */
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writel(0x1DFE, &dma4_cfg->chan[chan].csr);
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/* reset IRQ */
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writel((1 << chan), &dma4_cfg->irqstatus_l[0]);
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dma_active &= ~(1 << chan);
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}
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/* Set Source, Destination and Size of DMA transfer for the
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* specified channel.
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* PARAMETERS:
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* chan: channel to use
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* src: source of the transfer
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* dst: destination of the transfer
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* sze: Size of the transfer
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*
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* RETURN of non-zero means error */
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int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
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uint32_t sze)
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{
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if (check_channel(chan))
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return -EINVAL;
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/* CDSA0 */
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writel((uint32_t)src, &dma4_cfg->chan[chan].cssa);
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writel((uint32_t)dst, &dma4_cfg->chan[chan].cdsa);
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writel(sze, &dma4_cfg->chan[chan].cen);
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return 0;
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}
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/* Start the DMA transfer */
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int omap3_dma_start_transfer(uint32_t chan)
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{
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uint32_t val;
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if (check_channel(chan))
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return -EINVAL;
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val = readl(&dma4_cfg->chan[chan].ccr);
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/* Test for channel already in use */
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if (val & CCR_ENABLE_ENABLE)
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return -EBUSY;
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writel((val | CCR_ENABLE_ENABLE), &dma4_cfg->chan[chan].ccr);
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dma_active |= (1 << chan);
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debug("started transfer...\n");
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return 0;
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}
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/* Busy-waiting for a DMA transfer
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* This has to be called before another transfer is started
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* PARAMETER
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* chan: Channel to wait for
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*
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* RETURN of non-zero means error*/
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int omap3_dma_wait_for_transfer(uint32_t chan)
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{
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uint32_t val;
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if (!(dma_active & (1 << chan))) {
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val = readl(&dma4_cfg->irqstatus_l[0]);
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if (!(val & chan)) {
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debug("dma: The channel you are trying to wait for "
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"was never activated - ERROR\n");
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return -1; /* channel was never active */
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}
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}
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/* all irqs on line 0 */
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while (!(readl(&dma4_cfg->irqstatus_l[0]) & (1 << chan)))
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asm("nop");
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val = readl(&dma4_cfg->chan[chan].csr);
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if ((val & CSR_TRANS_ERR) | (val & CSR_SUPERVISOR_ERR) |
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(val & CSR_MISALIGNED_ADRS_ERR)) {
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debug("err code: %X\n", val);
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debug("dma: transfer error detected\n");
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reset_irq(chan);
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return -1;
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}
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reset_irq(chan);
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return 0;
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}
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/* Get the revision of the DMA module
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* PARAMETER
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* minor: Address of minor revision to write
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* major: Address of major revision to write
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*
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* RETURN of non-zero means error
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*/
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int omap3_dma_get_revision(uint32_t *minor, uint32_t *major)
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{
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uint32_t val;
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/* debug information */
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val = readl(&dma4_cfg->revision);
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*major = (val & 0x000000F0) >> 4;
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*minor = (val & 0x0000000F);
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debug("DMA Silicon revision (maj/min): 0x%X/0x%X\n", *major, *minor);
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return 0;
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}
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/* Initial config of omap dma
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*/
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void omap3_dma_init(void)
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{
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dma_active = 0;
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/* All interrupts on channel 0 */
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writel(0xFFFFFFFF, &dma4_cfg->irqenable_l[0]);
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}
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/* set channel config to config
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*
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* RETURN of non-zero means error */
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int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config)
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{
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if (check_channel(chan))
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return -EINVAL;
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dma4_cfg->chan[chan] = *config;
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return 0;
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}
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/* get channel config to config
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*
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* RETURN of non-zero means error */
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int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config)
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{
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if (check_channel(chan))
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return -EINVAL;
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*config = dma4_cfg->chan[chan];
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return 0;
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}
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