473 lines
14 KiB
C
473 lines
14 KiB
C
/*
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* (C) Copyright 2001-2002
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* Wolfgang Denk, DENX Software Engineering -- wd@denx.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/************************************************************************/
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/* ** HEADER FILES */
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/************************************************************************/
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/* #define DEBUG */
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <watchdog.h>
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#include <version.h>
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#include <stdarg.h>
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#include <lcdvideo.h>
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#include <linux/types.h>
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#include <stdio_dev.h>
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#if defined(CONFIG_POST)
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#include <post.h>
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#endif
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#include <lcd.h>
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#ifdef CONFIG_LCD
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/************************************************************************/
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/* ** CONFIG STUFF -- should be moved to board config file */
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/************************************************************************/
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#ifndef CONFIG_LCD_INFO
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#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
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#endif
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#if defined(CONFIG_EDT32F10)
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#undef CONFIG_LCD_LOGO
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#undef CONFIG_LCD_INFO
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#endif
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_KYOCERA_KCS057QV1AJ
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/*
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* Kyocera KCS057QV1AJ-G23. Passive, color, single scan.
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*/
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#define LCD_BPP LCD_COLOR4
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vidinfo_t panel_info = {
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640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
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LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_KYOCERA_KCS057QV1AJ */
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/*----------------------------------------------------------------------*/
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_HITACHI_SP19X001_Z1A
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/*
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* Hitachi SP19X001-. Active, color, single scan.
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*/
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vidinfo_t panel_info = {
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640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
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LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_HITACHI_SP19X001_Z1A */
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/*----------------------------------------------------------------------*/
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_NEC_NL6448AC33
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/*
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* NEC NL6448AC33-18. Active, color, single scan.
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*/
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vidinfo_t panel_info = {
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640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
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3, 0, 0, 1, 1, 144, 2, 0, 33
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_NEC_NL6448AC33 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_NEC_NL6448BC20
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/*
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* NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan.
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*/
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vidinfo_t panel_info = {
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640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
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3, 0, 0, 1, 1, 144, 2, 0, 33
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_NEC_NL6448BC20 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_NEC_NL6448BC33_54
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/*
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* NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan.
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*/
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vidinfo_t panel_info = {
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640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
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3, 0, 0, 1, 1, 144, 2, 0, 33
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_NEC_NL6448BC33_54 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_SHARP_LQ104V7DS01
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/*
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* SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan.
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*/
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vidinfo_t panel_info = {
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640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
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3, 0, 0, 1, 1, 25, 1, 0, 33
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_SHARP_LQ104V7DS01 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_SHARP_16x9
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/*
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* Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am
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* not sure what it is.......
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*/
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vidinfo_t panel_info = {
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320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
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3, 0, 0, 1, 1, 15, 4, 0, 3
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};
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#endif /* CONFIG_SHARP_16x9 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_SHARP_LQ057Q3DC02
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/*
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* Sharp LQ057Q3DC02 display. Active, color, single scan.
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*/
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#undef LCD_DF
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#define LCD_DF 12
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vidinfo_t panel_info = {
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320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
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3, 0, 0, 1, 1, 15, 4, 0, 3
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/* wbl, vpw, lcdac, wbf */
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};
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#define CONFIG_LCD_INFO_BELOW_LOGO
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#endif /* CONFIG_SHARP_LQ057Q3DC02 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_SHARP_LQ64D341
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/*
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* Sharp LQ64D341 display, 640x480. Active, color, single scan.
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*/
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vidinfo_t panel_info = {
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640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
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3, 0, 0, 1, 1, 128, 16, 0, 32
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_SHARP_LQ64D341 */
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#ifdef CONFIG_SHARP_LQ065T9DR51U
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/*
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* Sharp LQ065T9DR51U display, 400x240. Active, color, single scan.
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*/
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vidinfo_t panel_info = {
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400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH,
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3, 0, 0, 1, 1, 248, 4, 0, 35
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/* wbl, vpw, lcdac, wbf */
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};
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#define CONFIG_LCD_INFO_BELOW_LOGO
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#endif /* CONFIG_SHARP_LQ065T9DR51U */
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#ifdef CONFIG_SHARP_LQ084V1DG21
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/*
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* Sharp LQ084V1DG21 display, 640x480. Active, color, single scan.
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*/
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vidinfo_t panel_info = {
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640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW,
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3, 0, 0, 1, 1, 160, 3, 0, 48
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_SHARP_LQ084V1DG21 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_HLD1045
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/*
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* HLD1045 display, 640x480. Active, color, single scan.
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*/
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vidinfo_t panel_info = {
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640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
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3, 0, 0, 1, 1, 160, 3, 0, 48
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_HLD1045 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_PRIMEVIEW_V16C6448AC
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/*
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* Prime View V16C6448AC
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*/
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vidinfo_t panel_info = {
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640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH,
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3, 0, 0, 1, 1, 144, 2, 0, 35
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/* wbl, vpw, lcdac, wbf */
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};
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#endif /* CONFIG_PRIMEVIEW_V16C6448AC */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_OPTREX_BW
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/*
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* Optrex CBL50840-2 NF-FW 99 22 M5
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* or
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* Hitachi LMG6912RPFC-00T
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* or
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* Hitachi SP14Q002
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*
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* 320x240. Black & white.
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*/
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#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */
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/* 1 - 4 grey levels, 2 bpp */
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/* 2 - 16 grey levels, 4 bpp */
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vidinfo_t panel_info = {
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320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
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OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4
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};
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#endif /* CONFIG_OPTREX_BW */
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/*-----------------------------------------------------------------*/
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#ifdef CONFIG_EDT32F10
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/*
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* Emerging Display Technologies 320x240. Passive, monochrome, single scan.
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*/
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#define LCD_BPP LCD_MONOCHROME
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#define LCD_DF 10
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vidinfo_t panel_info = {
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320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW,
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LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0
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};
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#endif
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/************************************************************************/
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/* ----------------- chipset specific functions ----------------------- */
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/************************************************************************/
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/*
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* Calculate fb size for VIDEOLFB_ATAG.
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*/
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ulong calc_fbsize (void)
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{
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ulong size;
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int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
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size = line_length * panel_info.vl_row;
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return size;
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}
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void lcd_ctrl_init (void *lcdbase)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile lcd823_t *lcdp = &immr->im_lcd;
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uint lccrtmp;
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uint lchcr_hpc_tmp;
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/* Initialize the LCD control register according to the LCD
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* parameters defined. We do everything here but enable
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* the controller.
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*/
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lccrtmp = LCDBIT (LCCR_BNUM_BIT,
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(((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128));
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lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) |
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LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) |
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LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) |
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LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) |
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LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) |
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LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) |
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LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) |
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LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) |
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LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) |
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LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft);
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#if 0
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lccrtmp |= ((SIU_LEVEL5 / 2) << 12);
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lccrtmp |= LCCR_EIEN;
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#endif
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lcdp->lcd_lccr = lccrtmp;
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lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */
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/* Initialize LCD controller bus priorities.
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*/
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immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */
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/* set SHFT/CLOCK division factor 4
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* This needs to be set based upon display type and processor
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* speed. The TFT displays run about 20 to 30 MHz.
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* I was running 64 MHz processor speed.
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* The value for this divider must be chosen so the result is
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* an integer of the processor speed (i.e., divide by 3 with
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* 64 MHz would be bad).
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*/
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immr->im_clkrst.car_sccr &= ~0x1F;
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immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */
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#if !defined(CONFIG_EDT32F10)
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/* Enable LCD on port D.
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*/
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immr->im_ioport.iop_pdpar |= 0x1FFF;
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immr->im_ioport.iop_pddir |= 0x1FFF;
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/* Enable LCD_A/B/C on port B.
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*/
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immr->im_cpm.cp_pbpar |= 0x00005001;
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immr->im_cpm.cp_pbdir |= 0x00005001;
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#else
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/* Enable LCD on port D.
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*/
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immr->im_ioport.iop_pdpar |= 0x1DFF;
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immr->im_ioport.iop_pdpar &= ~0x0200;
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immr->im_ioport.iop_pddir |= 0x1FFF;
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immr->im_ioport.iop_pddat |= 0x0200;
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#endif
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/* Load the physical address of the linear frame buffer
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* into the LCD controller.
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* BIG NOTE: This has to be modified to load A and B depending
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* upon the split mode of the LCD.
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*/
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lcdp->lcd_lcfaa = (ulong)lcdbase;
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lcdp->lcd_lcfba = (ulong)lcdbase;
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/* MORE HACKS...This must be updated according to 823 manual
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* for different panels.
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* Udi Finkelstein - done - see below:
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* Note: You better not try unsupported combinations such as
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* 4-bit wide passive dual scan LCD at 4/8 Bit color.
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*/
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lchcr_hpc_tmp =
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(panel_info.vl_col *
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(panel_info.vl_tft ? 8 :
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(((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
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/* use << to mult by: single scan = 1, dual scan = 2 */
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panel_info.vl_splt) *
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(panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */
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lcdp->lcd_lchcr = LCHCR_BO |
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LCDBIT (LCHCR_AT_BIT, 4) |
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LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) |
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panel_info.vl_wbl;
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lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) |
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LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) |
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LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) |
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panel_info.vl_wbf;
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}
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/*----------------------------------------------------------------------*/
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#if LCD_BPP == LCD_COLOR8
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void
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lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cp = &(immr->im_cpm);
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unsigned short colreg, *cmap_ptr;
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cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2];
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colreg = ((red & 0x0F) << 8) |
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((green & 0x0F) << 4) |
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(blue & 0x0F) ;
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#ifdef CONFIG_SYS_INVERT_COLORS
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colreg ^= 0x0FFF;
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#endif
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*cmap_ptr = colreg;
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debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
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regno, &(cp->lcd_cmap[regno * 2]),
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red, green, blue,
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cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
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}
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#endif /* LCD_COLOR8 */
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/*----------------------------------------------------------------------*/
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#if LCD_BPP == LCD_MONOCHROME
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static
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void lcd_initcolregs (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cp = &(immr->im_cpm);
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ushort regno;
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for (regno = 0; regno < 16; regno++) {
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cp->lcd_cmap[regno * 2] = 0;
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cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f;
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}
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}
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#endif
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/*----------------------------------------------------------------------*/
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void lcd_enable (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile lcd823_t *lcdp = &immr->im_lcd;
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/* Enable the LCD panel */
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immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
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lcdp->lcd_lccr |= LCCR_PON;
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#if defined(CONFIG_LWMON)
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{ uchar c = pic_read (0x60);
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#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
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/* Enable LCD later in sysmon test, only if temperature is OK */
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#else
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c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
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#endif
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pic_write (0x60, c);
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}
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#endif /* CONFIG_LWMON */
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#if defined(CONFIG_R360MPI)
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{
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extern void r360_i2c_lcd_write (uchar data0, uchar data1);
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unsigned long bgi, ctr;
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char *p;
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if ((p = getenv("lcdbgi")) != NULL) {
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bgi = simple_strtoul (p, 0, 10) & 0xFFF;
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} else {
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bgi = 0xFFF;
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}
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if ((p = getenv("lcdctr")) != NULL) {
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ctr = simple_strtoul (p, 0, 10) & 0xFFF;
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} else {
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ctr=0x7FF;
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}
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r360_i2c_lcd_write(0x10, 0x01);
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r360_i2c_lcd_write(0x20, 0x01);
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r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF);
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r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF);
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}
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#endif /* CONFIG_R360MPI */
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#ifdef CONFIG_RRVISION
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debug ("PC4->Output(1): enable LVDS\n");
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debug ("PC5->Output(0): disable PAL clock\n");
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immr->im_ioport.iop_pddir |= 0x1000;
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immr->im_ioport.iop_pcpar &= ~(0x0C00);
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immr->im_ioport.iop_pcdir |= 0x0C00 ;
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immr->im_ioport.iop_pcdat |= 0x0800 ;
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immr->im_ioport.iop_pcdat &= ~(0x0400);
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debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
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immr->im_ioport.iop_pdpar,
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immr->im_ioport.iop_pddir,
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immr->im_ioport.iop_pddat);
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debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
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immr->im_ioport.iop_pcpar,
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immr->im_ioport.iop_pcdir,
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immr->im_ioport.iop_pcdat);
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#endif
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}
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|
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/************************************************************************/
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|
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#endif /* CONFIG_LCD */
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