420 lines
11 KiB
C
420 lines
11 KiB
C
/*
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* (C) Copyright 2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Author: Igor Lisitsin <igor@emcraft.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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/*
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* Ethernet test
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*
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* The Ethernet Media Access Controllers (EMAC) are tested in the
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* internal loopback mode.
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* The controllers are configured accordingly and several packets
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* are transmitted. The configurable test parameters are:
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* MIN_PACKET_LENGTH - minimum size of packet to transmit
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* MAX_PACKET_LENGTH - maximum size of packet to transmit
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* CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
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* is tested with a different frame length. Starting with
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* MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
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* Defaults to 10 and can be overriden in the board config header.
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*/
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_ETHER
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/ppc4xx-mal.h>
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#include <asm/ppc4xx-emac.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Get count of EMAC devices (doesn't have to be the max. possible number
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* supported by the cpu)
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*
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* CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
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* EMAC count is possible. As it is needed for the Kilauea/Haleakala
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* 405EX/405EXr eval board, using the same binary.
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*/
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#if defined(CONFIG_BOARD_EMAC_COUNT)
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#define LAST_EMAC_NUM board_emac_count()
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#else /* CONFIG_BOARD_EMAC_COUNT */
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#if defined(CONFIG_HAS_ETH3)
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#define LAST_EMAC_NUM 4
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#elif defined(CONFIG_HAS_ETH2)
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#define LAST_EMAC_NUM 3
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#elif defined(CONFIG_HAS_ETH1)
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#define LAST_EMAC_NUM 2
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#else
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#define LAST_EMAC_NUM 1
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#endif
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#endif /* CONFIG_BOARD_EMAC_COUNT */
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
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#endif
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#define MIN_PACKET_LENGTH 64
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#define MAX_PACKET_LENGTH 1514
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#ifndef CONFIG_SYS_POST_ETH_LOOPS
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#define CONFIG_SYS_POST_ETH_LOOPS 10
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#endif
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#define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
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CONFIG_SYS_POST_ETH_LOOPS)
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static volatile mal_desc_t tx __cacheline_aligned;
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static volatile mal_desc_t rx __cacheline_aligned;
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static char *tx_buf;
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static char *rx_buf;
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int board_emac_count(void);
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static void ether_post_init (int devnum, int hw_addr)
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{
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int i;
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#if defined(CONFIG_440GX) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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unsigned mode_reg;
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sys_info_t sysinfo;
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#endif
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
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unsigned long mfr;
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#endif
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#if defined(CONFIG_440GX) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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/* Need to get the OPB frequency so we can access the PHY */
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get_sys_info (&sysinfo);
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#endif
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* provide clocks for EMAC internal loopback */
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mfsdr (SDR0_MFR, mfr);
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mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
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mtsdr (SDR0_MFR, mfr);
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sync ();
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#endif
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/* reset emac */
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out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
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sync ();
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for (i = 0;; i++) {
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if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST))
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break;
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if (i >= 1000) {
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printf ("Timeout resetting EMAC\n");
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break;
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}
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udelay (1000);
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}
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#if defined(CONFIG_440GX) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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/* Whack the M1 register */
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mode_reg = 0x0;
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if (sysinfo.freqOPB <= 50000000);
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else if (sysinfo.freqOPB <= 66666667)
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mode_reg |= EMAC_MR1_OBCI_66;
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else if (sysinfo.freqOPB <= 83333333)
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mode_reg |= EMAC_MR1_OBCI_83;
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else if (sysinfo.freqOPB <= 100000000)
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mode_reg |= EMAC_MR1_OBCI_100;
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else
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mode_reg |= EMAC_MR1_OBCI_GT100;
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out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg);
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#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
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/* set the Mal configuration reg */
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#if defined(CONFIG_440GX) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE)
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mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
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MAL_CR_PLBLT_DEFAULT | 0x00330000);
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#else
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mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
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/* Errata 1.12: MAL_1 -- Disable MAL bursting */
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if (get_pvr() == PVR_440GP_RB) {
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mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
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}
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#endif
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/* setup buffer descriptors */
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tx.ctrl = MAL_TX_CTRL_WRAP;
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tx.data_len = 0;
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tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
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rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
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rx.data_len = 0;
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rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
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flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
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flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
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switch (devnum) {
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case 1:
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/* setup MAL tx & rx channel pointers */
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#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
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mtdcr (MAL0_TXCTP2R, &tx);
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#else
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mtdcr (MAL0_TXCTP1R, &tx);
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#endif
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#if defined(CONFIG_440)
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mtdcr (MAL0_TXBADDR, 0x0);
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mtdcr (MAL0_RXBADDR, 0x0);
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#endif
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mtdcr (MAL0_RXCTP1R, &rx);
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/* set RX buffer size */
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mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16);
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break;
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case 0:
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default:
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/* setup MAL tx & rx channel pointers */
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#if defined(CONFIG_440)
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mtdcr (MAL0_TXBADDR, 0x0);
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mtdcr (MAL0_RXBADDR, 0x0);
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#endif
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mtdcr (MAL0_TXCTP0R, &tx);
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mtdcr (MAL0_RXCTP0R, &rx);
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/* set RX buffer size */
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mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16);
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break;
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}
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/* Enable MAL transmit and receive channels */
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#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
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mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2)));
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#else
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mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum));
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#endif
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mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum));
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/* set internal loopback mode */
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#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
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out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 |
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EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
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EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
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in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
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#else
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out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE |
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EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K |
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EMAC_MR1_MF_100MBPS | EMAC_MR1_IST |
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in_be32 ((void*)(EMAC0_MR1 + hw_addr)));
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#endif
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/* set transmit enable & receive enable */
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out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE);
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/* enable broadcast address */
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out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE);
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/* set transmit request threshold register */
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out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */
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/* set receive low/high water mark register */
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#if defined(CONFIG_440)
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/* 440s has a 64 byte burst length */
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out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000);
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#else
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/* 405s have a 16 byte burst length */
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out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
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#endif /* defined(CONFIG_440) */
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out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000);
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/* Set fifo limit entry in tx mode 0 */
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out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003);
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/* Frame gap set */
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out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008);
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sync ();
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}
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static void ether_post_halt (int devnum, int hw_addr)
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{
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int i = 0;
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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unsigned long mfr;
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#endif
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/* 1st reset MAL channel */
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/* Note: writing a 0 to a channel has no effect */
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#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
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mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2));
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#else
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mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum);
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#endif
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mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum);
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/* wait for reset */
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while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) {
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if (i++ >= 1000)
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break;
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udelay (1000);
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}
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/* emac reset */
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out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST);
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* remove clocks for EMAC internal loopback */
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mfsdr (SDR0_MFR, mfr);
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mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
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mtsdr (SDR0_MFR, mfr);
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#endif
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}
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static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
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{
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int i = 0;
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while (tx.ctrl & MAL_TX_CTRL_READY) {
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if (i++ > 100) {
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printf ("TX timeout\n");
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return;
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}
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udelay (1000);
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invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
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}
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tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
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EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
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tx.data_len = length;
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memcpy (tx.data_ptr, packet, length);
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flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
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flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
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sync ();
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out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0);
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sync ();
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}
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static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
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{
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int length;
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int i = 0;
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while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
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if (i++ > 100) {
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printf ("RX timeout\n");
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return 0;
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}
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udelay (1000);
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invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
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}
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length = rx.data_len - 4;
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if (length <= max_length) {
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invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
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memcpy(packet, rx.data_ptr, length);
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}
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sync ();
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rx.ctrl |= MAL_RX_CTRL_EMPTY;
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flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
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sync ();
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return length;
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}
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/*
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* Test routines
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*/
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static void packet_fill (char *packet, int length)
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{
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char c = (char) length;
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int i;
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/* set up ethernet header */
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memset (packet, 0xff, 14);
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for (i = 14; i < length; i++) {
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packet[i] = c++;
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}
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}
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static int packet_check (char *packet, int length)
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{
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char c = (char) length;
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int i;
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for (i = 14; i < length; i++) {
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if (packet[i] != c++)
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return -1;
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}
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return 0;
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}
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char packet_send[MAX_PACKET_LENGTH];
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char packet_recv[MAX_PACKET_LENGTH];
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static int test_ctlr (int devnum, int hw_addr)
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{
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int res = -1;
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int length;
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int l;
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ether_post_init (devnum, hw_addr);
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for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
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l -= PACKET_INCR) {
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packet_fill (packet_send, l);
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ether_post_send (devnum, hw_addr, packet_send, l);
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length = ether_post_recv (devnum, hw_addr, packet_recv,
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sizeof (packet_recv));
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if (length != l || packet_check (packet_recv, length) < 0) {
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goto Done;
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}
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}
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res = 0;
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Done:
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ether_post_halt (devnum, hw_addr);
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if (res != 0) {
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post_log ("EMAC%d test failed\n", devnum);
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}
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return res;
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}
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int ether_post_test (int flags)
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{
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int res = 0;
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int i;
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/* Allocate tx & rx packet buffers */
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tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
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rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
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if (!tx_buf || !rx_buf) {
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printf ("Failed to allocate packet buffers\n");
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res = -1;
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goto out_free;
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}
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for (i = 0; i < LAST_EMAC_NUM; i++) {
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if (test_ctlr (i, i*0x100))
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res = -1;
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}
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out_free:
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free (tx_buf);
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free (rx_buf);
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return res;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */
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