213 lines
5.9 KiB
C
213 lines
5.9 KiB
C
/*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Authors:
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* Aneesh V <aneesh@ti.com>
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* Sricharan R <r.sricharan@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _OMAP5_H_
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#define _OMAP5_H_
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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/*
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* L4 Peripherals - L4 Wakeup and L4 Core now
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*/
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#define OMAP54XX_L4_CORE_BASE 0x4A000000
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#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
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#define OMAP54XX_L4_PER_BASE 0x48000000
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#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
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#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF
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#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
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#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
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/* CONTROL ID CODE */
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#define CONTROL_CORE_ID_CODE 0x4A002204
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#define CONTROL_WKUP_ID_CODE 0x4AE0C204
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#ifdef CONFIG_DRA7XX
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#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
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#else
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#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
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#endif
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/* To be verified */
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#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
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#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
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#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
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#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
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#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
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/* UART */
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#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
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#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
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#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
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/* General Purpose Timers */
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#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
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#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
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#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
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/* Watchdog Timer2 - MPU watchdog */
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#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
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/* GPMC */
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#define OMAP54XX_GPMC_BASE 0x50000000
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/*
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* Hardware Register Details
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*/
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/* Watchdog Timer */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* GP Timer */
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/* Control Module */
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#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
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#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
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#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
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#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
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/* LPDDR2 IO regs */
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#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
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#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
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#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
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#define LPDDR2IO_GR10_WD_MASK (3 << 17)
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#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
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/* CONTROL_EFUSE_2 */
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#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
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#define SDCARD_BIAS_PWRDNZ (1 << 27)
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#define SDCARD_PWRDNZ (1 << 26)
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#define SDCARD_BIAS_HIZ_MODE (1 << 25)
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#define SDCARD_PBIASLITE_VMODE (1 << 21)
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#ifndef __ASSEMBLY__
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struct s32ktimer {
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unsigned char res[0x10];
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unsigned int s32k_cr; /* 0x10 */
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};
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#define DEVICE_TYPE_SHIFT 0x6
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#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
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#define DEVICE_GP 0x3
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/* Output impedance control */
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#define ds_120_ohm 0x0
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#define ds_60_ohm 0x1
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#define ds_45_ohm 0x2
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#define ds_30_ohm 0x3
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#define ds_mask 0x3
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/* Slew rate control */
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#define sc_slow 0x0
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#define sc_medium 0x1
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#define sc_fast 0x2
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#define sc_na 0x3
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#define sc_mask 0x3
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/* Target capacitance control */
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#define lb_5_12_pf 0x0
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#define lb_12_25_pf 0x1
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#define lb_25_50_pf 0x2
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#define lb_50_80_pf 0x3
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#define lb_mask 0x3
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#define usb_i_mask 0x7
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#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082
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#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
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#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
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#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
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#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
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#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
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#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
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#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
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#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
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#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
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#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
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#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
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#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
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#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
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#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
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#define EFUSE_1 0x45145100
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#define EFUSE_2 0x45145100
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#define EFUSE_3 0x45145100
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#define EFUSE_4 0x45145100
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_DRA7XX
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#define NON_SECURE_SRAM_START 0x40300000
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#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
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#else
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#define NON_SECURE_SRAM_START 0x40300000
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#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
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#endif
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#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
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/* base address for indirect vectors (internal boot mode) */
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#define SRAM_ROM_VECT_BASE 0x4031F000
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/* CONTROL_SRCOMP_XXX_SIDE */
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#define OVERRIDE_XS_SHIFT 30
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#define OVERRIDE_XS_MASK (1 << 30)
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#define SRCODE_READ_XS_SHIFT 12
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#define SRCODE_READ_XS_MASK (0xff << 12)
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#define PWRDWN_XS_SHIFT 11
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#define PWRDWN_XS_MASK (1 << 11)
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#define DIVIDE_FACTOR_XS_SHIFT 4
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#define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
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#define MULTIPLY_FACTOR_XS_SHIFT 1
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#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
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#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
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#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
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/* ABB settings */
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#define OMAP_ABB_SETTLING_TIME 50
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#define OMAP_ABB_CLOCK_CYCLES 16
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/* ABB tranxdone mask */
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#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
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/* ABB efuse masks */
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#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24)
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#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29)
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#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
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#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)
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#ifndef __ASSEMBLY__
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struct srcomp_params {
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s8 divide_factor;
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s8 multiply_factor;
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};
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struct ctrl_ioregs {
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u32 ctrl_ddrch;
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u32 ctrl_lpddr2ch;
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u32 ctrl_ddr3ch;
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u32 ctrl_ddrio_0;
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u32 ctrl_ddrio_1;
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u32 ctrl_ddrio_2;
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u32 ctrl_emif_sdram_config_ext;
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u32 ctrl_ddr_ctrl_ext_0;
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};
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#endif /* __ASSEMBLY__ */
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#endif
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