145 lines
2.3 KiB
C
145 lines
2.3 KiB
C
/*
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* Copyright (C) 2012 Andes Technology Corporation
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
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{
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if (cache == ICACHE)
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return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
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>> ICM_CFG_OFF_ISZ) - 1);
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else
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return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
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>> DCM_CFG_OFF_DSZ) - 1);
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(DCACHE);
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while (end > start) {
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asm volatile (
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"\n\tcctl %0, L1D_VA_WB"
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"\n\tcctl %0, L1D_VA_INVAL"
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:
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: "r" (start)
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);
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start += line_size;
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}
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}
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void invalidate_icache_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(ICACHE);
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while (end > start) {
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asm volatile (
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"\n\tcctl %0, L1I_VA_INVAL"
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:
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: "r"(start)
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);
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start += line_size;
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}
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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unsigned long line_size;
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line_size = CACHE_LINE_SIZE(DCACHE);
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while (end > start) {
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asm volatile (
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"\n\tcctl %0, L1D_VA_INVAL"
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:
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: "r"(start)
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);
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start += line_size;
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}
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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flush_dcache_range(addr, addr + size);
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invalidate_icache_range(addr, addr + size);
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}
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void icache_enable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x01\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void icache_disable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x01\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int icache_status(void)
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{
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int ret;
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x01\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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void dcache_enable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"ori $p0, $p0, 0x02\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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void dcache_disable(void)
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{
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"li $p1, ~0x02\n\t"
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"and $p0, $p0, $p1\n\t"
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"mtsr $p0, $mr8\n\t"
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"isb\n\t"
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);
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}
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int dcache_status(void)
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{
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int ret;
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asm volatile (
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"mfsr $p0, $mr8\n\t"
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"andi %0, $p0, 0x02\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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return ret;
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}
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