17 lines
533 B
C
17 lines
533 B
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Virtex2 FPGA configuration support for the QUANTUM computer
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*/
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int fpga_boot(unsigned char *fpgadata, int size);
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#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
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#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
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#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
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