404 lines
10 KiB
C
404 lines
10 KiB
C
/*
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* (C) Copyright 2001-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <config.h>
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#include <mpc8xx.h>
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#include <i2c.h>
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#include <commproc.h>
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#include <command.h>
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#include <malloc.h>
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#include <linux/types.h>
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#include <linux/string.h> /* for strdup */
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/*
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* Memory Controller Using
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*
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* CS0 - Flash memory (0x40000000)
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* CS1 - FLASH memory (0x????????)
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* CS2 - SDRAM (0x00000000)
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* CS3 -
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* CS4 -
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* CS5 -
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* CS6 - PCMCIA device
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* CS7 - PCMCIA device
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*/
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/* ------------------------------------------------------------------------- */
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#define _not_used_ 0xffffffff
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const uint sdram_table[]=
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{
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/* single read. (offset 0 in upm RAM) */
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0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
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0x1ff77c47,
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/* MRS initialization (offset 5) */
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0x1ff77c34, 0xefeabc34, 0x1fb57c35,
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/* burst read. (offset 8 in upm RAM) */
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0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
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0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* single write. (offset 18 in upm RAM) */
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0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* burst write. (offset 20 in upm RAM) */
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0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
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0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* refresh. (offset 30 in upm RAM) */
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0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
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_not_used_, _not_used_, _not_used_, _not_used_,
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/* exception. (offset 3c in upm RAM) */
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0x7ffffc07, _not_used_, _not_used_, _not_used_ };
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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puts ("Board: R360 MPI Board\n");
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size8, size9;
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long int size_b0 = 0;
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unsigned long reg;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller bank 2 to the SDRAM bank at
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* preliminary address - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
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memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
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udelay (200);
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memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
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udelay (200);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 2 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size_b0 = size9;
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/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
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} else { /* back to 8 columns */
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size_b0 = size8;
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
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udelay (500);
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/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
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}
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type, both banks
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if ((size_b0 < 0x02000000)) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
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udelay (1000);
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}
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/*
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* Final mapping
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*/
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memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
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memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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udelay (10000);
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#ifdef CONFIG_CAN_DRIVER
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/* Initialize OR3 / BR3 */
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memctl->memc_or3 = CONFIG_SYS_OR3_CAN; /* switch GPLB_5 to GPLA_5 */
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memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
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/* Initialize MBMR */
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memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */
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/* Initialize UPMB for CAN: single read */
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memctl->memc_mdr = 0xFFFFC004;
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memctl->memc_mcr = 0x0100 | UPMB;
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memctl->memc_mdr = 0x0FFFD004;
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memctl->memc_mcr = 0x0101 | UPMB;
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memctl->memc_mdr = 0x0FFFC000;
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memctl->memc_mcr = 0x0102 | UPMB;
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memctl->memc_mdr = 0x3FFFC004;
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memctl->memc_mcr = 0x0103 | UPMB;
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memctl->memc_mdr = 0xFFFFDC05;
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memctl->memc_mcr = 0x0104 | UPMB;
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/* Initialize UPMB for CAN: single write */
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memctl->memc_mdr = 0xFFFCC004;
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memctl->memc_mcr = 0x0118 | UPMB;
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memctl->memc_mdr = 0xCFFCD004;
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memctl->memc_mcr = 0x0119 | UPMB;
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memctl->memc_mdr = 0x0FFCC000;
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memctl->memc_mcr = 0x011A | UPMB;
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memctl->memc_mdr = 0x7FFCC004;
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memctl->memc_mcr = 0x011B | UPMB;
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memctl->memc_mdr = 0xFFFDCC05;
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memctl->memc_mcr = 0x011C | UPMB;
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#endif
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return (size_b0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value,
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long int *base, long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size(base, maxsize));
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}
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/* ------------------------------------------------------------------------- */
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void r360_i2c_lcd_write (uchar data0, uchar data1)
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{
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if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
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printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
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}
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}
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/* ------------------------------------------------------------------------- */
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/*-----------------------------------------------------------------------
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* Keyboard Controller
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*/
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/* Number of bytes returned from Keyboard Controller */
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#define KEYBD_KEY_MAX 16 /* maximum key number */
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#define KEYBD_DATALEN ((KEYBD_KEY_MAX + 7) / 8) /* normal key scan data */
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static uchar *key_match (uchar *);
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int misc_init_r (void)
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{
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char kbd_data[KEYBD_DATALEN];
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char keybd_env[2 * KEYBD_DATALEN + 1];
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char *str;
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int i;
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i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
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for (i = 0; i < KEYBD_DATALEN; ++i) {
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sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
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}
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setenv ("keybd", keybd_env);
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str = strdup ((char *)key_match ((uchar *)keybd_env)); /* decode keys */
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#ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
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setenv ("preboot", str); /* set or delete definition */
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#endif /* CONFIG_PREBOOT */
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if (str != NULL) {
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free (str);
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}
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return (0);
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}
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/*-----------------------------------------------------------------------
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* Check if pressed key(s) match magic sequence,
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* and return the command string associated with that key(s).
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*
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* If no key press was decoded, NULL is returned.
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*
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* Note: the first character of the argument will be overwritten with
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* the "magic charcter code" of the decoded key(s), or '\0'.
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*
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*
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* Note: the string points to static environment data and must be
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* saved before you call any function that modifies the environment.
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*/
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#ifdef CONFIG_PREBOOT
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static uchar kbd_magic_prefix[] = "key_magic";
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static uchar kbd_command_prefix[] = "key_cmd";
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static uchar *key_match (uchar * kbd_str)
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{
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uchar magic[sizeof (kbd_magic_prefix) + 1];
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uchar cmd_name[sizeof (kbd_command_prefix) + 1];
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uchar *str, *suffix;
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uchar *kbd_magic_keys;
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char *cmd;
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/*
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* The following string defines the characters that can pe appended
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* to "key_magic" to form the names of environment variables that
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* hold "magic" key codes, i. e. such key codes that can cause
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* pre-boot actions. If the string is empty (""), then only
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* "key_magic" is checked (old behaviour); the string "125" causes
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* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
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*/
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if ((kbd_magic_keys = (uchar *)getenv ("magic_keys")) != NULL) {
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/* loop over all magic keys;
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* use '\0' suffix in case of empty string
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*/
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for (suffix = kbd_magic_keys;
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*suffix || suffix == kbd_magic_keys;
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++suffix) {
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sprintf ((char *)magic, "%s%c", kbd_magic_prefix, *suffix);
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#if 0
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printf ("### Check magic \"%s\"\n", magic);
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#endif
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if ((str = (uchar *)getenv ((char *)magic)) != 0) {
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#if 0
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printf ("### Compare \"%s\" \"%s\"\n",
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kbd_str, str);
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#endif
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if (strcmp ((char *)kbd_str, (char *)str) == 0) {
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sprintf ((char *)cmd_name, "%s%c",
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kbd_command_prefix,
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*suffix);
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if ((cmd = getenv ((char *)cmd_name)) != 0) {
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#if 0
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printf ("### Set PREBOOT to $(%s): \"%s\"\n",
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cmd_name, cmd);
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#endif
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return ((uchar *)cmd);
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}
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}
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}
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}
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}
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#if 0
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printf ("### Delete PREBOOT\n");
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#endif
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*kbd_str = '\0';
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return (NULL);
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}
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#endif /* CONFIG_PREBOOT */
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/* Read Keyboard status */
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int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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uchar kbd_data[KEYBD_DATALEN];
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uchar keybd_env[2 * KEYBD_DATALEN + 1];
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int i;
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i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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/* Read keys */
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i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
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puts ("Keys:");
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for (i = 0; i < KEYBD_DATALEN; ++i) {
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sprintf ((char *)(keybd_env + i + i), "%02X", kbd_data[i]);
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printf (" %02x", kbd_data[i]);
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}
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putc ('\n');
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setenv ("keybd", (char *)keybd_env);
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return 0;
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}
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U_BOOT_CMD(
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kbd, 1, 1, do_kbd,
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"read keyboard status",
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""
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);
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