388 lines
9.1 KiB
C
388 lines
9.1 KiB
C
/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* CPU specific code for the MPC83xx family.
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*
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* Derived from the MPC8260 and MPC85xx.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <mpc83xx.h>
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#include <asm/processor.h>
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#include <libfdt.h>
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#include <tsec.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkcpu(void)
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{
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volatile immap_t *immr;
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ulong clock = gd->cpu_clk;
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u32 pvr = get_pvr();
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u32 spridr;
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char buf[32];
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int i;
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const struct cpu_type {
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char name[15];
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u32 partid;
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} cpu_type_list [] = {
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CPU_TYPE_ENTRY(8311),
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CPU_TYPE_ENTRY(8313),
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CPU_TYPE_ENTRY(8314),
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CPU_TYPE_ENTRY(8315),
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CPU_TYPE_ENTRY(8321),
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CPU_TYPE_ENTRY(8323),
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CPU_TYPE_ENTRY(8343),
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CPU_TYPE_ENTRY(8347_TBGA_),
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CPU_TYPE_ENTRY(8347_PBGA_),
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CPU_TYPE_ENTRY(8349),
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CPU_TYPE_ENTRY(8358_TBGA_),
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CPU_TYPE_ENTRY(8358_PBGA_),
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CPU_TYPE_ENTRY(8360),
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CPU_TYPE_ENTRY(8377),
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CPU_TYPE_ENTRY(8378),
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CPU_TYPE_ENTRY(8379),
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};
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immr = (immap_t *)CONFIG_SYS_IMMR;
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puts("CPU: ");
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switch (pvr & 0xffff0000) {
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case PVR_E300C1:
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printf("e300c1, ");
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break;
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case PVR_E300C2:
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printf("e300c2, ");
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break;
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case PVR_E300C3:
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printf("e300c3, ");
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break;
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case PVR_E300C4:
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printf("e300c4, ");
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break;
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default:
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printf("Unknown core, ");
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}
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spridr = immr->sysconf.spridr;
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
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puts("MPC");
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puts(cpu_type_list[i].name);
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if (IS_E_PROCESSOR(spridr))
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puts("E");
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if (REVID_MAJOR(spridr) >= 2)
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puts("A");
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printf(", Rev: %d.%d", REVID_MAJOR(spridr),
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REVID_MINOR(spridr));
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break;
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}
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if (i == ARRAY_SIZE(cpu_type_list))
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printf("(SPRIDR %08x unknown), ", spridr);
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printf(" at %s MHz, ", strmhz(buf, clock));
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printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
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return 0;
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}
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/*
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* Program a UPM with the code supplied in the table.
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*
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* The 'dummy' variable is used to increment the MAD. 'dummy' is
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* supposed to be a pointer to the memory of the device being
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* programmed by the UPM. The data in the MDR is written into
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* memory and the MAD is incremented every time there's a write
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* to 'dummy'. Unfortunately, the current prototype for this
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* function doesn't allow for passing the address of this
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* device, and changing the prototype will break a number lots
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* of other code, so we need to use a round-about way of finding
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* the value for 'dummy'.
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*
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* The value can be extracted from the base address bits of the
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* Base Register (BR) associated with the specific UPM. To find
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* that BR, we need to scan all 8 BRs until we find the one that
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* has its MSEL bits matching the UPM we want. Once we know the
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* right BR, we can extract the base address bits from it.
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*
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* The MxMR and the BR and OR of the chosen bank should all be
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* configured before calling this function.
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*
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* Parameters:
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* upm: 0=UPMA, 1=UPMB, 2=UPMC
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* table: Pointer to an array of values to program
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* size: Number of elements in the array. Must be 64 or less.
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*/
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void upmconfig (uint upm, uint *table, uint size)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile fsl_lbus_t *lbus = &immap->lbus;
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volatile uchar *dummy = NULL;
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const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
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volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
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uint i;
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/* Scan all the banks to determine the base address of the device */
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for (i = 0; i < 8; i++) {
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if ((lbus->bank[i].br & BR_MSEL) == msel) {
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dummy = (uchar *) (lbus->bank[i].br & BR_BA);
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break;
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}
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}
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if (!dummy) {
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printf("Error: %s() could not find matching BR\n", __FUNCTION__);
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hang();
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}
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/* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
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*mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
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for (i = 0; i < size; i++) {
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lbus->mdr = table[i];
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__asm__ __volatile__ ("sync");
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*dummy = 0; /* Write the value to memory and increment MAD */
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__asm__ __volatile__ ("sync");
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while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
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}
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/* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
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*mxmr &= 0xCFFFFFC0;
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}
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int
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do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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ulong msr;
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#ifndef MPC83xx_RESET
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ulong addr;
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#endif
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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#ifdef MPC83xx_RESET
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~( MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/* enable Reset Control Reg */
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immap->reset.rpr = 0x52535445;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* confirm Reset Control Reg is enabled */
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while(!((immap->reset.rcer) & RCER_CRE));
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printf("Resetting the board.");
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printf("\n");
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udelay(200);
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/* perform reset, only one bit */
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immap->reset.rcr = RCR_SWHR;
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#else /* ! MPC83xx_RESET */
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immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/*
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* Trying to execute the next instruction at a non-existing address
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* should cause a machine check, resulting in reset
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*/
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addr = CONFIG_SYS_RESET_ADDRESS;
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printf("resetting the board.");
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printf("\n");
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((void (*)(void)) addr) ();
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#endif /* MPC83xx_RESET */
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return 1;
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}
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/*
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* Get timebase clock frequency (like cpu_clk in Hz)
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*/
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unsigned long get_tbclk(void)
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{
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ulong tbclk;
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tbclk = (gd->bus_clk + 3L) / 4L;
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return tbclk;
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}
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#if defined(CONFIG_WATCHDOG)
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void watchdog_reset (void)
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{
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int re_enable = disable_interrupts();
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/* Reset the 83xx watchdog */
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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immr->wdt.swsrr = 0x556c;
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immr->wdt.swsrr = 0xaa39;
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if (re_enable)
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enable_interrupts ();
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}
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#endif
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#if defined(CONFIG_DDR_ECC)
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void dma_init(void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile dma83xx_t *dma = &immap->dma;
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volatile u32 status = swab32(dma->dmasr0);
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volatile u32 dmamr0 = swab32(dma->dmamr0);
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debug("DMA-init\n");
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/* initialize DMASARn, DMADAR and DMAABCRn */
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dma->dmadar0 = (u32)0;
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dma->dmasar0 = (u32)0;
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dma->dmabcr0 = 0;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* clear CS bit */
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dmamr0 &= ~DMA_CHANNEL_START;
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dma->dmamr0 = swab32(dmamr0);
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* while the channel is busy, spin */
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while(status & DMA_CHANNEL_BUSY) {
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status = swab32(dma->dmasr0);
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}
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debug("DMA-init end\n");
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}
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uint dma_check(void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile dma83xx_t *dma = &immap->dma;
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volatile u32 status = swab32(dma->dmasr0);
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volatile u32 byte_count = swab32(dma->dmabcr0);
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/* while the channel is busy, spin */
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while (status & DMA_CHANNEL_BUSY) {
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status = swab32(dma->dmasr0);
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}
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if (status & DMA_CHANNEL_TRANSFER_ERROR) {
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printf ("DMA Error: status = %x @ %d\n", status, byte_count);
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}
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return status;
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}
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int dma_xfer(void *dest, u32 count, void *src)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile dma83xx_t *dma = &immap->dma;
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volatile u32 dmamr0;
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/* initialize DMASARn, DMADAR and DMAABCRn */
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dma->dmadar0 = swab32((u32)dest);
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dma->dmasar0 = swab32((u32)src);
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dma->dmabcr0 = swab32(count);
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* init direct transfer, clear CS bit */
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dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
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DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
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DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
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dma->dmamr0 = swab32(dmamr0);
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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/* set CS to start DMA transfer */
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dmamr0 |= DMA_CHANNEL_START;
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dma->dmamr0 = swab32(dmamr0);
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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return ((int)dma_check());
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}
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#endif /*CONFIG_DDR_ECC*/
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_UEC_ETH1)
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uec_initialize(0);
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#endif
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#if defined(CONFIG_UEC_ETH2)
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uec_initialize(1);
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#endif
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#if defined(CONFIG_UEC_ETH3)
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uec_initialize(2);
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#endif
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#if defined(CONFIG_UEC_ETH4)
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uec_initialize(3);
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#endif
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#if defined(CONFIG_UEC_ETH5)
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uec_initialize(4);
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#endif
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#if defined(CONFIG_UEC_ETH6)
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uec_initialize(5);
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#endif
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#if defined(CONFIG_TSEC_ENET)
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tsec_standard_init(bis);
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#endif
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return 0;
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}
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