74 lines
2.4 KiB
C
74 lines
2.4 KiB
C
/*
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* Copyright (C) 2013 Boundary Devices Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MX6_DDR_H__
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#define __ASM_ARCH_MX6_DDR_H__
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#ifdef CONFIG_MX6Q
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#include "mx6q-ddr.h"
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#else
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#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
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#include "mx6dl-ddr.h"
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#else
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#error "Please select cpu"
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#endif /* CONFIG_MX6DL or CONFIG_MX6S */
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#endif /* CONFIG_MX6Q */
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#define MX6_MMDC_P0_MDCTL 0x021b0000
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#define MX6_MMDC_P0_MDPDC 0x021b0004
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#define MX6_MMDC_P0_MDOTC 0x021b0008
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#define MX6_MMDC_P0_MDCFG0 0x021b000c
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#define MX6_MMDC_P0_MDCFG1 0x021b0010
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#define MX6_MMDC_P0_MDCFG2 0x021b0014
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#define MX6_MMDC_P0_MDMISC 0x021b0018
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#define MX6_MMDC_P0_MDSCR 0x021b001c
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#define MX6_MMDC_P0_MDREF 0x021b0020
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#define MX6_MMDC_P0_MDRWD 0x021b002c
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#define MX6_MMDC_P0_MDOR 0x021b0030
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#define MX6_MMDC_P0_MDASP 0x021b0040
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#define MX6_MMDC_P0_MAPSR 0x021b0404
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#define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
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#define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
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#define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
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#define MX6_MMDC_P0_MPODTCTRL 0x021b0818
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#define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
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#define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
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#define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
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#define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
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#define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
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#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
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#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
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#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
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#define MX6_MMDC_P0_MPMUR0 0x021b08b8
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#define MX6_MMDC_P1_MDCTL 0x021b4000
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#define MX6_MMDC_P1_MDPDC 0x021b4004
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#define MX6_MMDC_P1_MDOTC 0x021b4008
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#define MX6_MMDC_P1_MDCFG0 0x021b400c
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#define MX6_MMDC_P1_MDCFG1 0x021b4010
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#define MX6_MMDC_P1_MDCFG2 0x021b4014
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#define MX6_MMDC_P1_MDMISC 0x021b4018
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#define MX6_MMDC_P1_MDSCR 0x021b401c
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#define MX6_MMDC_P1_MDREF 0x021b4020
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#define MX6_MMDC_P1_MDRWD 0x021b402c
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#define MX6_MMDC_P1_MDOR 0x021b4030
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#define MX6_MMDC_P1_MDASP 0x021b4040
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#define MX6_MMDC_P1_MAPSR 0x021b4404
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#define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
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#define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
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#define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
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#define MX6_MMDC_P1_MPODTCTRL 0x021b4818
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#define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
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#define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
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#define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
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#define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
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#define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
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#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
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#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
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#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
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#define MX6_MMDC_P1_MPMUR0 0x021b48b8
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#endif /*__ASM_ARCH_MX6_DDR_H__ */
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