34 lines
871 B
C
34 lines
871 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Xilinx, Inc.
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*/
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#ifndef _ZYNQ_BOOTIMG_H_
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#define _ZYNQ_BOOTIMG_H_
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#define ZYNQ_MAX_PARTITION_NUMBER 0xE
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struct partition_hdr {
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u32 imagewordlen; /* 0x0 */
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u32 datawordlen; /* 0x4 */
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u32 partitionwordlen; /* 0x8 */
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u32 loadaddr; /* 0xC */
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u32 execaddr; /* 0x10 */
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u32 partitionstart; /* 0x14 */
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u32 partitionattr; /* 0x18 */
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u32 sectioncount; /* 0x1C */
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u32 checksumoffset; /* 0x20 */
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u32 pads1[1];
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u32 acoffset; /* 0x28 */
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u32 pads2[4];
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u32 checksum; /* 0x3C */
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};
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int zynq_get_part_count(struct partition_hdr *part_hdr_info);
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int zynq_get_partition_info(u32 image_base_addr, u32 *fsbl_len,
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struct partition_hdr *part_hdr);
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int zynq_validate_hdr(struct partition_hdr *header);
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int zynq_validate_partition(u32 start_addr, u32 len, u32 chksum_off);
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#endif /* _ZYNQ_BOOTIMG_H_ */
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