37ad8377af
The PLL1 node (st,pll1) is optional in device tree, the max supported frequency define in OPP node is used when the node is absent. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> |
||
|---|---|---|
| .. | ||
| fixed-factor-clock.txt | ||
| fsl,mpc83xx-clk.txt | ||
| microchip,pic32-clock.txt | ||
| nvidia,tegra20-car.txt | ||
| rockchip,rk3188-cru.txt | ||
| rockchip,rk3288-cru.txt | ||
| rockchip,rk3288-dmc.txt | ||
| rockchip,rk3368-dmc.txt | ||
| rockchip,rk3399-dmc.txt | ||
| rockchip.txt | ||
| snps,hsdk-cgu.txt | ||
| st,stm32-rcc.txt | ||
| st,stm32h7-rcc.txt | ||
| st,stm32mp1.txt | ||
| ti,cdce9xx.txt | ||
| ti,sci-clk.txt | ||