113 lines
2.5 KiB
ArmAsm
113 lines
2.5 KiB
ArmAsm
/*
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* armboot - Startup Code for ARM1176 CPU-core
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*
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* Copyright (c) 2007 Samsung Electronics
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*
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* Copyright (C) 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
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* 2007-09-21 - Added MoviNAND and OneNAND boot codes by
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* jsgood (jsgood.yang@samsung.com)
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* Base codes by scsuh (sc.suh)
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#ifndef CONFIG_SYS_PHY_UBOOT_BASE
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#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
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#endif
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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.globl reset
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0, cpsr
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bic r0, r0, #0x3f
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orr r0, r0, #0xd3
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msr cpsr, r0
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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cpu_init_crit:
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/*
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* When booting from NAND - it has definitely been a reset, so, no need
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* to flush caches and disable the MMU
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*/
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#ifndef CONFIG_SPL_BUILD
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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/* Prepare to disable the MMU */
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adr r2, mmu_disable_phys
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sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
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b mmu_disable
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.align 5
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/* Run in a single cache-line */
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mmu_disable:
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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mov pc, r2
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mmu_disable_phys:
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#endif
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/*
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* Go setup Memory and board specific bits prior to relocation.
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*/
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bl lowlevel_init /* go setup pll,mux,memory */
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bl _main
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/*------------------------------------------------------------------------------*/
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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mov pc, lr
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