108 lines
2.1 KiB
C
108 lines
2.1 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_ifc.h>
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#include <nand.h>
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#include <spl.h>
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#include <asm/arch-fsl-lsch3/soc.h>
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#include <asm/io.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void erratum_a008751(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
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u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
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writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
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#endif
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}
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static void erratum_rcw_src(void)
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{
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#if defined(CONFIG_SPL)
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u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
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u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
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u32 val;
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val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
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val &= ~DCFG_PORSR1_RCW_SRC;
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val |= DCFG_PORSR1_RCW_SRC_NOR;
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out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
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#endif
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}
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#define I2C_DEBUG_REG 0x6
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#define I2C_GLITCH_EN 0x8
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/*
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* This erratum requires setting glitch_en bit to enable
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* digital glitch filter to improve clock stability.
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*/
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static void erratum_a009203(void)
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{
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u8 __iomem *ptr;
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#ifdef CONFIG_SYS_I2C
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#ifdef I2C1_BASE_ADDR
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ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C2_BASE_ADDR
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ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C3_BASE_ADDR
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ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C4_BASE_ADDR
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ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#endif
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}
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void fsl_lsch3_early_init_f(void)
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{
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erratum_a008751();
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erratum_rcw_src();
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init_early_memctl_regs(); /* tighten IFC timing */
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erratum_a009203();
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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/* Clear global data */
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memset((void *)gd, 0, sizeof(gd_t));
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arch_cpu_init();
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board_early_init_f();
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timer_init();
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env_init();
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gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
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serial_init();
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console_init_f();
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dram_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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board_init_r(NULL, 0);
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_NAND;
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}
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#endif
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