41 lines
662 B
Plaintext
41 lines
662 B
Plaintext
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/* First 4KB has trampoline code for secondary cores. */
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/memreserve/ 0x00000000 0x0001000;
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#include "socfpga.dtsi"
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/ {
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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mmc0: dwmmc0@ff704000 {
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num-slots = <1>;
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broken-cd;
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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};
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ethernet@ff702000 {
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phy-mode = "rgmii";
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phy-addr = <0xffffffff>; /* probe for phy addr */
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status = "okay";
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};
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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};
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};
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