451 lines
10 KiB
Plaintext
451 lines
10 KiB
Plaintext
#include <dt-bindings/clock/tegra20-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra20";
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interrupt-parent = <&intc>;
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host1x {
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compatible = "nvidia,tegra20-host1x", "simple-bus";
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reg = <0x50000000 0x00024000>;
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interrupts = <0 65 0x04 /* mpcore syncpt */
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0 67 0x04>; /* mpcore general */
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x54000000 0x54000000 0x04000000>;
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/* video-encoding/decoding */
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mpe {
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reg = <0x54040000 0x00040000>;
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interrupts = <0 68 0x04>;
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status = "disabled";
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};
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/* video input */
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vi {
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reg = <0x54080000 0x00040000>;
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interrupts = <0 69 0x04>;
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status = "disabled";
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};
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/* EPP */
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epp {
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reg = <0x540c0000 0x00040000>;
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interrupts = <0 70 0x04>;
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status = "disabled";
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};
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/* ISP */
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isp {
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reg = <0x54100000 0x00040000>;
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interrupts = <0 71 0x04>;
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status = "disabled";
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};
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/* 2D engine */
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gr2d {
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reg = <0x54140000 0x00040000>;
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interrupts = <0 72 0x04>;
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status = "disabled";
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};
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/* 3D engine */
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gr3d {
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reg = <0x54180000 0x00040000>;
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status = "disabled";
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};
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/* display controllers */
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dc@54200000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54200000 0x00040000>;
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interrupts = <0 73 0x04>;
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status = "disabled";
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rgb {
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status = "disabled";
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};
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};
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dc@54240000 {
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compatible = "nvidia,tegra20-dc";
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reg = <0x54240000 0x00040000>;
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interrupts = <0 74 0x04>;
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status = "disabled";
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rgb {
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status = "disabled";
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};
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};
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/* outputs */
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hdmi {
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compatible = "nvidia,tegra20-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <0 75 0x04>;
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status = "disabled";
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};
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tvo {
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compatible = "nvidia,tegra20-tvo";
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reg = <0x542c0000 0x00040000>;
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interrupts = <0 76 0x04>;
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status = "disabled";
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};
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dsi {
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compatible = "nvidia,tegra20-dsi";
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reg = <0x54300000 0x00040000>;
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status = "disabled";
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};
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};
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intc: interrupt-controller@50041000 {
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compatible = "nvidia,tegra20-gic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = < 0x50041000 0x1000 >,
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< 0x50040100 0x0100 >;
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};
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra20-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1200>;
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interrupts = <0 104 0x04
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0 105 0x04
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0 106 0x04
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0 107 0x04
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0 108 0x04
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0 109 0x04
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0 110 0x04
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0 111 0x04
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0 112 0x04
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0 113 0x04
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0 114 0x04
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0 115 0x04
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0 116 0x04
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0 117 0x04
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0 118 0x04
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0 119 0x04>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra20-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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pinmux: pinmux@70000000 {
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compatible = "nvidia,tegra20-pinmux";
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reg = < 0x70000014 0x10 /* Tri-state registers */
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0x70000080 0x20 /* Mux registers */
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0x700000a0 0x14 /* Pull-up/down registers */
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0x70000868 0xa8 >; /* Pad control registers */
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};
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das@70000c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-das";
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reg = <0x70000c00 0x80>;
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};
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i2s@70002800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002800 0x200>;
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interrupts = < 45 >;
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dma-channel = < 2 >;
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};
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i2s@70002a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002a00 0x200>;
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interrupts = < 35 >;
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dma-channel = < 1 >;
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};
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uarta: serial@70006000 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA20_CLK_UARTA>;
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resets = <&tegra_car 6>;
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reset-names = "serial";
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dmas = <&apbdma 8>, <&apbdma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartb: serial@70006040 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA20_CLK_UARTB>;
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resets = <&tegra_car 7>;
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reset-names = "serial";
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dmas = <&apbdma 9>, <&apbdma 9>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartc: serial@70006200 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA20_CLK_UARTC>;
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resets = <&tegra_car 55>;
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reset-names = "serial";
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dmas = <&apbdma 10>, <&apbdma 10>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uartd: serial@70006300 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA20_CLK_UARTD>;
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resets = <&tegra_car 65>;
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reset-names = "serial";
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dmas = <&apbdma 19>, <&apbdma 19>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uarte: serial@70006400 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA20_CLK_UARTE>;
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resets = <&tegra_car 66>;
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reset-names = "serial";
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dmas = <&apbdma 20>, <&apbdma 20>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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nand: nand-controller@70008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-nand";
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reg = <0x70008000 0x100>;
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};
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pwm: pwm@7000a000 {
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compatible = "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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};
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i2c@7000c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C000 0x100>;
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interrupts = < 70 >;
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/* PERIPH_ID_I2C1, PLL_P_OUT3 */
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clocks = <&tegra_car 12>, <&tegra_car 124>;
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};
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spi@7000c380 {
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compatible = "nvidia,tegra20-sflash";
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reg = <0x7000c380 0x80>;
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interrupts = <0 39 0x04>;
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nvidia,dma-request-selector = <&apbdma 11>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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/* PERIPH_ID_SPI1, PLLP_OUT0 */
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clocks = <&tegra_car 43>;
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};
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i2c@7000c400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C400 0x100>;
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interrupts = < 116 >;
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/* PERIPH_ID_I2C2, PLL_P_OUT3 */
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clocks = <&tegra_car 54>, <&tegra_car 124>;
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};
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i2c@7000c500 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C500 0x100>;
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interrupts = < 124 >;
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/* PERIPH_ID_I2C3, PLL_P_OUT3 */
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clocks = <&tegra_car 67>, <&tegra_car 124>;
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};
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i2c@7000d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c-dvc";
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reg = <0x7000D000 0x200>;
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interrupts = < 85 >;
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/* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
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clocks = <&tegra_car 47>, <&tegra_car 124>;
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};
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kbc@7000e200 {
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compatible = "nvidia,tegra20-kbc";
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reg = <0x7000e200 0x0078>;
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};
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emc@7000f400 {
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#address-cells = < 1 >;
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#size-cells = < 0 >;
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compatible = "nvidia,tegra20-emc";
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reg = <0x7000f400 0x200>;
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};
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pcie-controller@80003000 {
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compatible = "nvidia,tegra20-pcie";
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device_type = "pci";
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reg = <0x80003000 0x00000800 /* PADS registers */
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0x80003800 0x00000200 /* AFI registers */
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0x90000000 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
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GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
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0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
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0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
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0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
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clocks = <&tegra_car TEGRA20_CLK_PEX>,
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<&tegra_car TEGRA20_CLK_AFI>,
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<&tegra_car TEGRA20_CLK_PCIE_XCLK>,
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<&tegra_car TEGRA20_CLK_PLL_E>;
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clock-names = "pex", "afi", "pcie_xclk", "pll_e";
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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};
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usb@c5000000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5000000 0x4000>;
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interrupts = < 52 >;
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phy_type = "utmi";
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clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
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nvidia,has-legacy-mode;
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};
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usb@c5004000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5004000 0x4000>;
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interrupts = < 53 >;
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phy_type = "ulpi";
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clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
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};
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usb@c5008000 {
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compatible = "nvidia,tegra20-ehci", "usb-ehci";
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reg = <0xc5008000 0x4000>;
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interrupts = < 129 >;
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phy_type = "utmi";
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clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
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};
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sdhci@c8000000 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000000 0x200>;
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interrupts = <0 14 0x04>;
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clocks = <&tegra_car 14>;
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status = "disabled";
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};
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sdhci@c8000200 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000200 0x200>;
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interrupts = <0 15 0x04>;
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clocks = <&tegra_car 9>;
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status = "disabled";
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};
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sdhci@c8000400 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000400 0x200>;
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interrupts = <0 19 0x04>;
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clocks = <&tegra_car 69>;
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status = "disabled";
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};
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sdhci@c8000600 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000600 0x200>;
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interrupts = <0 31 0x04>;
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clocks = <&tegra_car 15>;
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status = "disabled";
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};
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};
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