103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/*
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* Copyright (C) 2014 Atmel
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* Bo Shen <voice.shen@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/sama5_matrix.h>
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#include <asm/arch/sama5_sfr.h>
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#include <asm/arch/sama5d4.h>
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char *get_cpu_name()
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{
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unsigned int extension_id = get_extension_chip_id();
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if (cpu_is_sama5d4())
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switch (extension_id) {
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case ARCH_EXID_SAMA5D41:
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return "SAMA5D41";
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case ARCH_EXID_SAMA5D42:
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return "SAMA5D42";
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case ARCH_EXID_SAMA5D43:
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return "SAMA5D43";
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case ARCH_EXID_SAMA5D44:
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return "SAMA5D44";
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default:
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return "Unknown CPU type";
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}
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else
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return "Unknown CPU type";
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}
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#ifdef CONFIG_USB_GADGET_ATMEL_USBA
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void at91_udp_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable UPLL clock */
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writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
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/* Enable UDPHS clock */
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at91_periph_clk_enable(ATMEL_ID_UDPHS);
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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void matrix_init(void)
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{
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struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
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struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
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int i;
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/* Disable the write protect */
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writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
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writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
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/* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
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for (i = 4; i <= 10; i++) {
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writel(0x000f0f0f, &h64mx->ssr[i]);
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writel(0x0000ffff, &h64mx->sassr[i]);
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writel(0x0000000f, &h64mx->srtsr[i]);
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}
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/* CS3 */
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writel(0x00c0c0c0, &h32mx->ssr[3]);
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writel(0xff000000, &h32mx->sassr[3]);
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writel(0xff000000, &h32mx->srtsr[3]);
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/* NFC SRAM */
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writel(0x00010101, &h32mx->ssr[4]);
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writel(0x00000001, &h32mx->sassr[4]);
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writel(0x00000001, &h32mx->srtsr[4]);
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/* Configure Programmable Security peripherals on matrix 64 */
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writel(readl(&h64mx->spselr[0]) | 0x00080000, &h64mx->spselr[0]);
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writel(readl(&h64mx->spselr[1]) | 0x00180000, &h64mx->spselr[1]);
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writel(readl(&h64mx->spselr[2]) | 0x00000008, &h64mx->spselr[2]);
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/* Configure Programmable Security peripherals on matrix 32 */
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writel(readl(&h32mx->spselr[0]) | 0xFFC00000, &h32mx->spselr[0]);
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writel(readl(&h32mx->spselr[1]) | 0x60E3FFFF, &h32mx->spselr[1]);
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/* Enable the write protect */
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writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
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writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
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}
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void redirect_int_from_saic_to_aic(void)
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{
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struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
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u32 key32;
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if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
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key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
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writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
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}
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}
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#endif
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