127 lines
2.9 KiB
C
127 lines
2.9 KiB
C
/*
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Low Power Divider specifications
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*/
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#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
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#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
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#define CLOCK_PLL_FVCO_MAX 540000000
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#define CLOCK_PLL_FVCO_MIN 300000000
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#define CLOCK_PLL_FSYS_MAX 266666666
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#define CLOCK_PLL_FSYS_MIN 100000000
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#define MHZ 1000000
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void clock_enter_limp(int lpdiv)
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{
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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int i, j;
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/* Check bounds of divider */
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if (lpdiv < CLOCK_LPD_MIN)
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lpdiv = CLOCK_LPD_MIN;
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if (lpdiv > CLOCK_LPD_MAX)
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lpdiv = CLOCK_LPD_MAX;
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/* Round divider down to nearest power of two */
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for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
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/* Apply the divider to the system clock */
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clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
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/* Enable Limp Mode */
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setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
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}
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/*
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* brief Exit Limp mode
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* warning The PLL should be set and locked prior to exiting Limp mode
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*/
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void clock_exit_limp(void)
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{
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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pll_t *pll = (pll_t *)MMAP_PLL;
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/* Exit Limp mode */
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clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
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/* Wait for the PLL to lock */
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while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
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;
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}
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/*
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* get_clocks() fills in gd->cpu_clock and gd->bus_clk
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*/
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int get_clocks(void)
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{
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ccm_t *ccm = (ccm_t *)MMAP_CCM;
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pll_t *pll = (pll_t *)MMAP_PLL;
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int vco, temp, pcrvalue, pfdr;
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u8 bootmode;
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pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
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pfdr = pcrvalue >> 24;
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if (pfdr == 0x1E)
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bootmode = 0; /* Normal Mode */
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#ifdef CONFIG_CF_SBF
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bootmode = 3; /* Serial Mode */
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#endif
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if (bootmode == 0) {
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/* Normal mode */
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vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
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if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
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/* Default value */
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pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
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pcrvalue |= 0x1E << 24;
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out_be32(&pll->pcr, pcrvalue);
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vco =
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((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
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CONFIG_SYS_INPUT_CLKSRC;
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}
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gd->arch.vco_clk = vco; /* Vco clock */
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} else if (bootmode == 3) {
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/* serial mode */
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vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
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gd->arch.vco_clk = vco; /* Vco clock */
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}
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if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
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/* Limp mode */
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} else {
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gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
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temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
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gd->cpu_clk = vco / temp; /* cpu clock */
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temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
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gd->arch.flb_clk = vco / temp; /* flexbus clock */
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gd->bus_clk = gd->arch.flb_clk;
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}
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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#endif
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return (0);
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}
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