358 lines
9.7 KiB
C
358 lines
9.7 KiB
C
/*
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*(C) Copyright 2005-2009 Netstal Maschinen AG
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* Bruno Hars (Bruno.Hars@netstal.com)
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* Niklaus Giger (Niklaus.Giger@netstal.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* reginfo.c - register dump of HW-configuratin register for PPC4xx based board
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-uic.h>
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#include <asm/ppc4xx-emac.h>
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enum REGISTER_TYPE {
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IDCR1, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */
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IDCR2, /* Indirectly Accessed DCR via EBC0_CFGADDR/EBC0_CFGDATA */
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IDCR3, /* Indirectly Accessed DCR via EBM0_CFGADDR/EBM0_CFGDATA */
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IDCR4, /* Indirectly Accessed DCR via PPM0_CFGADDR/PPM0_CFGDATA */
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IDCR5, /* Indirectly Accessed DCR via CPR0_CFGADDR/CPR0_CFGDATA */
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IDCR6, /* Indirectly Accessed DCR via SDR0_CFGADDR/SDR0_CFGDATA */
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MM /* Directly Accessed MMIO Register */
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};
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struct cpu_register {
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char *name;
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enum REGISTER_TYPE type;
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u32 address;
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};
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/*
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* PPC440EPx registers ordered for output
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* name type addr size
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* -------------------------------------------
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*/
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const struct cpu_register ppc4xx_reg[] = {
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{"PB0CR", IDCR2, PB0CR},
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{"PB0AP", IDCR2, PB0AP},
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{"PB1CR", IDCR2, PB1CR},
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{"PB1AP", IDCR2, PB1AP},
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{"PB2CR", IDCR2, PB2CR},
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{"PB2AP", IDCR2, PB2AP},
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{"PB3CR", IDCR2, PB3CR},
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{"PB3AP", IDCR2, PB3AP},
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{"PB4CR", IDCR2, PB4CR},
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{"PB4AP", IDCR2, PB4AP},
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#if !defined(CONFIG_405EP)
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{"PB5CR", IDCR2, PB5CR},
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{"PB5AP", IDCR2, PB5AP},
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{"PB6CR", IDCR2, PB6CR},
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{"PB6AP", IDCR2, PB6AP},
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{"PB7CR", IDCR2, PB7CR},
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{"PB7AP", IDCR2, PB7AP},
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#endif
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{"PBEAR", IDCR2, PBEAR},
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#if defined(CONFIG_405EP) || defined (CONFIG_405GP)
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{"PBESR0", IDCR2, PBESR0},
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{"PBESR1", IDCR2, PBESR1},
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#endif
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{"EBC0_CFG", IDCR2, EBC0_CFG},
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#ifdef CONFIG_405GP
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{"SDRAM0_BESR0", IDCR1, SDRAM0_BESR0},
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{"SDRAM0_BESRS0", IDCR1, SDRAM0_BESRS0},
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{"SDRAM0_BESR1", IDCR1, SDRAM0_BESR1},
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{"SDRAM0_BESRS1", IDCR1, SDRAM0_BESRS1},
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{"SDRAM0_BEAR", IDCR1, SDRAM0_BEAR},
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{"SDRAM0_CFG", IDCR1, SDRAM0_CFG},
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{"SDRAM0_RTR", IDCR1, SDRAM0_RTR},
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{"SDRAM0_PMIT", IDCR1, SDRAM0_PMIT},
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{"SDRAM0_B0CR", IDCR1, SDRAM0_B0CR},
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{"SDRAM0_B1CR", IDCR1, SDRAM0_B1CR},
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{"SDRAM0_B2CR", IDCR1, SDRAM0_B2CR},
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{"SDRAM0_B3CR", IDCR1, SDRAM0_B1CR},
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{"SDRAM0_TR", IDCR1, SDRAM0_TR},
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{"SDRAM0_ECCCFG", IDCR1, SDRAM0_B1CR},
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{"SDRAM0_ECCESR", IDCR1, SDRAM0_ECCESR},
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#endif
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#ifdef CONFIG_440EPX
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{"SDR0_SDSTP0", IDCR6, SDR0_SDSTP0},
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{"SDR0_SDSTP1", IDCR6, SDR0_SDSTP1},
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{"SDR0_SDSTP2", IDCR6, SDR0_SDSTP2},
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{"SDR0_SDSTP3", IDCR6, SDR0_SDSTP3},
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{"SDR0_CUST0", IDCR6, SDR0_CUST0},
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{"SDR0_CUST1", IDCR6, SDR0_CUST1},
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{"SDR0_EBC", IDCR6, SDR0_EBC},
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{"SDR0_AMP0", IDCR6, SDR0_AMP0},
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{"SDR0_AMP1", IDCR6, SDR0_AMP1},
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{"SDR0_CP440", IDCR6, SDR0_CP440},
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{"SDR0_CRYP0", IDCR6, SDR0_CRYP0},
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{"SDR0_DDRCFG", IDCR6, SDR0_DDRCFG},
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{"SDR0_EMAC0RXST", IDCR6, SDR0_EMAC0RXST},
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{"SDR0_EMAC0TXST", IDCR6, SDR0_EMAC0TXST},
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{"SDR0_MFR", IDCR6, SDR0_MFR},
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{"SDR0_PCI0", IDCR6, SDR0_PCI0},
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{"SDR0_PFC0", IDCR6, SDR0_PFC0},
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{"SDR0_PFC1", IDCR6, SDR0_PFC1},
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{"SDR0_PFC2", IDCR6, SDR0_PFC2},
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{"SDR0_PFC4", IDCR6, SDR0_PFC4},
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{"SDR0_UART0", IDCR6, SDR0_UART0},
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{"SDR0_UART1", IDCR6, SDR0_UART1},
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{"SDR0_UART2", IDCR6, SDR0_UART2},
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{"SDR0_UART3", IDCR6, SDR0_UART3},
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{"DDR0_02", IDCR1, DDR0_02},
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{"DDR0_00", IDCR1, DDR0_00},
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{"DDR0_01", IDCR1, DDR0_01},
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{"DDR0_03", IDCR1, DDR0_03},
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{"DDR0_04", IDCR1, DDR0_04},
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{"DDR0_05", IDCR1, DDR0_05},
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{"DDR0_06", IDCR1, DDR0_06},
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{"DDR0_07", IDCR1, DDR0_07},
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{"DDR0_08", IDCR1, DDR0_08},
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{"DDR0_09", IDCR1, DDR0_09},
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{"DDR0_10", IDCR1, DDR0_10},
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{"DDR0_11", IDCR1, DDR0_11},
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{"DDR0_12", IDCR1, DDR0_12},
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{"DDR0_14", IDCR1, DDR0_14},
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{"DDR0_17", IDCR1, DDR0_17},
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{"DDR0_18", IDCR1, DDR0_18},
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{"DDR0_19", IDCR1, DDR0_19},
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{"DDR0_20", IDCR1, DDR0_20},
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{"DDR0_21", IDCR1, DDR0_21},
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{"DDR0_22", IDCR1, DDR0_22},
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{"DDR0_23", IDCR1, DDR0_23},
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{"DDR0_24", IDCR1, DDR0_24},
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{"DDR0_25", IDCR1, DDR0_25},
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{"DDR0_26", IDCR1, DDR0_26},
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{"DDR0_27", IDCR1, DDR0_27},
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{"DDR0_28", IDCR1, DDR0_28},
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{"DDR0_31", IDCR1, DDR0_31},
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{"DDR0_32", IDCR1, DDR0_32},
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{"DDR0_33", IDCR1, DDR0_33},
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{"DDR0_34", IDCR1, DDR0_34},
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{"DDR0_35", IDCR1, DDR0_35},
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{"DDR0_36", IDCR1, DDR0_36},
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{"DDR0_37", IDCR1, DDR0_37},
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{"DDR0_38", IDCR1, DDR0_38},
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{"DDR0_39", IDCR1, DDR0_39},
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{"DDR0_40", IDCR1, DDR0_40},
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{"DDR0_41", IDCR1, DDR0_41},
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{"DDR0_42", IDCR1, DDR0_42},
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{"DDR0_43", IDCR1, DDR0_43},
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{"DDR0_44", IDCR1, DDR0_44},
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{"CPR0_ICFG", IDCR5, CPR0_ICFG},
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{"CPR0_MALD", IDCR5, CPR0_MALD},
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{"CPR0_OPBD00", IDCR5, CPR0_OPBD0},
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{"CPR0_PERD0", IDCR5, CPR0_PERD},
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{"CPR0_PLLC0", IDCR5, CPR0_PLLC},
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{"CPR0_PLLD0", IDCR5, CPR0_PLLD},
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{"CPR0_PRIMAD0", IDCR5, CPR0_PRIMAD0},
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{"CPR0_PRIMBD0", IDCR5, CPR0_PRIMBD0},
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{"CPR0_SPCID", IDCR5, CPR0_SPCID},
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{"SPI0_MODE", MM, SPI0_MODE},
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{"IIC0_CLKDIV", MM, PCIL0_PMM1MA},
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{"PCIL0_PMM0MA", MM, PCIL0_PMM0MA},
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{"PCIL0_PMM1MA", MM, PCIL0_PMM1MA},
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{"PCIL0_PTM1LA", MM, PCIL0_PMM1MA},
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{"PCIL0_PTM1MS", MM, PCIL0_PTM1MS},
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{"PCIL0_PTM2LA", MM, PCIL0_PMM1MA},
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{"PCIL0_PTM2MS", MM, PCIL0_PTM2MS},
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{"ZMII0_FER", MM, ZMII0_FER},
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{"ZMII0_SSR", MM, ZMII0_SSR},
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{"EMAC0_IPGVR", MM, EMAC0_IPGVR},
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{"EMAC0_MR1", MM, EMAC0_MR1},
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{"EMAC0_PTR", MM, EMAC0_PTR},
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{"EMAC0_RWMR", MM, EMAC0_RWMR},
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{"EMAC0_STACR", MM, EMAC0_STACR},
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{"EMAC0_TMR0", MM, EMAC0_TMR0},
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{"EMAC0_TMR1", MM, EMAC0_TMR1},
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{"EMAC0_TRTR", MM, EMAC0_TRTR},
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{"EMAC1_MR1", MM, EMAC1_MR1},
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{"GPIO0_OR", MM, GPIO0_OR},
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{"GPIO1_OR", MM, GPIO1_OR},
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{"GPIO0_TCR", MM, GPIO0_TCR},
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{"GPIO1_TCR", MM, GPIO1_TCR},
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{"GPIO0_ODR", MM, GPIO0_ODR},
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{"GPIO1_ODR", MM, GPIO1_ODR},
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{"GPIO0_OSRL", MM, GPIO0_OSRL},
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{"GPIO0_OSRH", MM, GPIO0_OSRH},
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{"GPIO1_OSRL", MM, GPIO1_OSRL},
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{"GPIO1_OSRH", MM, GPIO1_OSRH},
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{"GPIO0_TSRL", MM, GPIO0_TSRL},
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{"GPIO0_TSRH", MM, GPIO0_TSRH},
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{"GPIO1_TSRL", MM, GPIO1_TSRL},
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{"GPIO1_TSRH", MM, GPIO1_TSRH},
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{"GPIO0_IR", MM, GPIO0_IR},
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{"GPIO1_IR", MM, GPIO1_IR},
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{"GPIO0_ISR1L", MM, GPIO0_ISR1L},
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{"GPIO0_ISR1H", MM, GPIO0_ISR1H},
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{"GPIO1_ISR1L", MM, GPIO1_ISR1L},
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{"GPIO1_ISR1H", MM, GPIO1_ISR1H},
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{"GPIO0_ISR2L", MM, GPIO0_ISR2L},
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{"GPIO0_ISR2H", MM, GPIO0_ISR2H},
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{"GPIO1_ISR2L", MM, GPIO1_ISR2L},
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{"GPIO1_ISR2H", MM, GPIO1_ISR2H},
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{"GPIO0_ISR3L", MM, GPIO0_ISR3L},
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{"GPIO0_ISR3H", MM, GPIO0_ISR3H},
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{"GPIO1_ISR3L", MM, GPIO1_ISR3L},
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{"GPIO1_ISR3H", MM, GPIO1_ISR3H},
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{"SDR0_USB2PHY0CR", IDCR6, SDR0_USB2PHY0CR},
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{"SDR0_USB2H0CR", IDCR6, SDR0_USB2H0CR},
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{"SDR0_USB2D0CR", IDCR6, SDR0_USB2D0CR},
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#endif
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};
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/*
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* CPU Register dump of PPC4xx HW configuration registers
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* Output: first all DCR-registers, then in order of struct ppc4xx_reg
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*/
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#define PRINT_DCR(dcr) printf("0x%08x %-16s: 0x%08x\n", dcr,#dcr, mfdcr(dcr));
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void ppc4xx_reginfo(void)
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{
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unsigned int i;
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unsigned int n;
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u32 value;
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enum REGISTER_TYPE type;
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#if defined (CONFIG_405EP)
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printf("Dump PPC405EP HW configuration registers\n\n");
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#elif CONFIG_405GP
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printf ("Dump 405GP HW configuration registers\n\n");
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#elif CONFIG_440EPX
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printf("Dump PPC440EPx HW configuration registers\n\n");
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#endif
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printf("MSR: 0x%08x\n", mfmsr());
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printf ("\nUniversal Interrupt Controller Regs\n");
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PRINT_DCR(UIC0SR);
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PRINT_DCR(UIC0ER);
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PRINT_DCR(UIC0CR);
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PRINT_DCR(UIC0PR);
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PRINT_DCR(UIC0TR);
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PRINT_DCR(UIC0MSR);
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PRINT_DCR(UIC0VR);
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PRINT_DCR(UIC0VCR);
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#if (UIC_MAX > 1)
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PRINT_DCR(UIC2SR);
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PRINT_DCR(UIC2ER);
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PRINT_DCR(UIC2CR);
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PRINT_DCR(UIC2PR);
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PRINT_DCR(UIC2TR);
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PRINT_DCR(UIC2MSR);
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PRINT_DCR(UIC2VR);
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PRINT_DCR(UIC2VCR);
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#endif
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#if (UIC_MAX > 2)
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PRINT_DCR(UIC2SR);
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PRINT_DCR(UIC2ER);
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PRINT_DCR(UIC2CR);
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PRINT_DCR(UIC2PR);
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PRINT_DCR(UIC2TR);
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PRINT_DCR(UIC2MSR);
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PRINT_DCR(UIC2VR);
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PRINT_DCR(UIC2VCR);
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#endif
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#if (UIC_MAX > 3)
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PRINT_DCR(UIC3SR);
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PRINT_DCR(UIC3ER);
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PRINT_DCR(UIC3CR);
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PRINT_DCR(UIC3PR);
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PRINT_DCR(UIC3TR);
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PRINT_DCR(UIC3MSR);
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PRINT_DCR(UIC3VR);
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PRINT_DCR(UIC3VCR);
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#endif
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#if defined (CONFIG_405EP) || defined (CONFIG_405GP)
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printf ("\n\nDMA Channels\n");
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PRINT_DCR(DMASR);
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PRINT_DCR(DMASGC);
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PRINT_DCR(DMAADR);
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PRINT_DCR(DMACR0);
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PRINT_DCR(DMACT0);
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PRINT_DCR(DMADA0);
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PRINT_DCR(DMASA0);
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PRINT_DCR(DMASB0);
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PRINT_DCR(DMACR1);
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PRINT_DCR(DMACT1);
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PRINT_DCR(DMADA1);
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PRINT_DCR(DMASA1);
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PRINT_DCR(DMASB1);
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PRINT_DCR(DMACR2);
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PRINT_DCR(DMACT2);
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PRINT_DCR(DMADA2);
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PRINT_DCR(DMASA2);
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PRINT_DCR(DMASB2);
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PRINT_DCR(DMACR3);
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PRINT_DCR(DMACT3);
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PRINT_DCR(DMADA3);
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PRINT_DCR(DMASA3);
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PRINT_DCR(DMASB3);
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#endif
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printf ("\n\nVarious HW-Configuration registers\n");
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#if defined (CONFIG_440EPX)
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PRINT_DCR(MAL0_CFG);
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PRINT_DCR(CPM0_ER);
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PRINT_DCR(CPM1_ER);
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PRINT_DCR(PLB4A0_ACR);
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PRINT_DCR(PLB4A1_ACR);
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PRINT_DCR(PLB3A0_ACR);
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PRINT_DCR(OPB2PLB40_BCTRL);
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PRINT_DCR(P4P3BO0_CFG);
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#endif
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n = sizeof(ppc4xx_reg) / sizeof(ppc4xx_reg[0]);
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for (i = 0; i < n; i++) {
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value = 0;
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type = ppc4xx_reg[i].type;
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switch (type) {
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case IDCR1: /* Indirect via SDRAM0_CFGADDR/DDR0_CFGDATA */
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mtdcr(SDRAM0_CFGADDR, ppc4xx_reg[i].address);
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value = mfdcr(SDRAM0_CFGDATA);
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break;
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case IDCR2: /* Indirect via EBC0_CFGADDR/EBC0_CFGDATA */
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mtdcr(EBC0_CFGADDR, ppc4xx_reg[i].address);
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value = mfdcr(EBC0_CFGDATA);
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break;
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case IDCR5: /* Indirect via CPR0_CFGADDR/CPR0_CFGDATA */
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mtdcr(CPR0_CFGADDR, ppc4xx_reg[i].address);
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value = mfdcr(CPR0_CFGDATA);
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break;
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case IDCR6: /* Indirect via SDR0_CFGADDR/SDR0_CFGDATA */
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mtdcr(SDR0_CFGADDR, ppc4xx_reg[i].address);
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value = mfdcr(SDR0_CFGDATA);
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break;
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case MM: /* Directly Accessed MMIO Register */
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value = in_be32((const volatile unsigned __iomem *)
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ppc4xx_reg[i].address);
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break;
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default:
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printf("\nERROR: struct entry %d: unknown register"
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"type\n", i);
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break;
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}
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printf("0x%08x %-16s: 0x%08x\n",ppc4xx_reg[i].address,
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ppc4xx_reg[i].name, value);
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}
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}
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