17 lines
391 B
C
17 lines
391 B
C
/*
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* Copyright (C) 2007 Semihalf
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* Written by Marian Balakowicz <m8@semihalf.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define SDRAM_DDR 1 /* is DDR */
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/* Settings for XLB = 132 MHz */
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#define SDRAM_MODE 0x018D0000
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#define SDRAM_EMODE 0x40090000
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#define SDRAM_CONTROL 0x714F0F00
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#define SDRAM_CONFIG1 0x73722930
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#define SDRAM_CONFIG2 0x46770000
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#define SDRAM_TAPDELAY 0x10000000
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