31 lines
589 B
C
31 lines
589 B
C
/*
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* Keystone2: DDR3 initialization
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include "ddr3_cfg.h"
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#include <asm/arch/ddr3.h>
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static struct pll_init_data ddr3_400 = DDR3_PLL_400;
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u32 ddr3_init(void)
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{
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init_pll(&ddr3_400);
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/* No SO-DIMM, 2GB discreet DDR */
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printf("DRAM: 2 GiB\n");
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/* Reset DDR3 PHY after PLL enabled */
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ddr3_reset_ddrphy();
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ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
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ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
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return 2;
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}
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