162 lines
3.5 KiB
C
162 lines
3.5 KiB
C
/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* This is a board specific file. It's OK to include board specific
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* header files */
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#include <common.h>
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#include <config.h>
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#include <fdtdec.h>
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#include <netdev.h>
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#include <asm/processor.h>
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#include <asm/microblaze_intc.h>
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#include <asm/asm.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_XILINX_GPIO
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static int reset_pin = -1;
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#endif
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#ifdef CONFIG_OF_CONTROL
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ulong ram_base;
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = ram_base;
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gd->bd->bi_dram[0].size = get_effective_memsize();
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}
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int dram_init(void)
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{
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int node;
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fdt_addr_t addr;
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fdt_size_t size;
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const void *blob = gd->fdt_blob;
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node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
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"memory", 7);
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if (node == -FDT_ERR_NOTFOUND) {
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debug("DRAM: Can't get memory node\n");
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return 1;
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}
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addr = fdtdec_get_addr_size(blob, node, "reg", &size);
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if (addr == FDT_ADDR_T_NONE || size == 0) {
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debug("DRAM: Can't get base address or size\n");
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return 1;
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}
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ram_base = addr;
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gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */
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gd->ram_size = size;
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return 0;
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};
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#else
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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#endif
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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#ifdef CONFIG_XILINX_GPIO
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if (reset_pin != -1)
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gpio_direction_output(reset_pin, 1);
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#endif
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#ifdef CONFIG_XILINX_TB_WATCHDOG
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hw_watchdog_disable();
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#endif
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puts ("Reseting board\n");
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__asm__ __volatile__ (" mts rmsr, r0;" \
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"bra r0");
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return 0;
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}
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int gpio_init (void)
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{
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#ifdef CONFIG_XILINX_GPIO
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reset_pin = gpio_alloc(CONFIG_SYS_GPIO_0_ADDR, "reset", 1);
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if (reset_pin != -1)
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gpio_request(reset_pin, "reset_pin");
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#endif
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return 0;
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}
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void board_init(void)
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{
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gpio_init();
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}
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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#ifdef CONFIG_XILINX_AXIEMAC
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ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
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XILINX_AXIDMA_BASEADDR);
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#endif
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#if defined(CONFIG_XILINX_EMACLITE) && defined(XILINX_EMACLITE_BASEADDR)
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u32 txpp = 0;
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u32 rxpp = 0;
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# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
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txpp = 1;
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# endif
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# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
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rxpp = 1;
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# endif
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ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
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txpp, rxpp);
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#endif
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#ifdef CONFIG_XILINX_LL_TEMAC
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# ifdef XILINX_LLTEMAC_BASEADDR
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# ifdef XILINX_LLTEMAC_FIFO_BASEADDR
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
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XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
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# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
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# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
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XILINX_LL_TEMAC_M_SDMA_DCR,
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XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
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# else
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
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XILINX_LL_TEMAC_M_SDMA_PLB,
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XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
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# endif
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# endif
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# endif
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# ifdef XILINX_LLTEMAC_BASEADDR1
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# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
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XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
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# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
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# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
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XILINX_LL_TEMAC_M_SDMA_DCR,
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XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
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# else
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ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
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XILINX_LL_TEMAC_M_SDMA_PLB,
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XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
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# endif
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# endif
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# endif
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#endif
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return ret;
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}
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