291 lines
8.3 KiB
C
291 lines
8.3 KiB
C
/*
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* Copyright (C) 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* qbman_sys_decl.h and qbman_sys.h are the two platform-specific files in the
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* driver. They are only included via qbman_private.h, which is itself a
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* platform-independent file and is included by all the other driver source.
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*
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* qbman_sys_decl.h is included prior to all other declarations and logic, and
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* it exists to provide compatibility with any linux interfaces our
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* single-source driver code is dependent on (eg. kmalloc). Ie. this file
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* provides linux compatibility.
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*
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* This qbman_sys.h header, on the other hand, is included *after* any common
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* and platform-neutral declarations and logic in qbman_private.h, and exists to
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* implement any platform-specific logic of the qbman driver itself. Ie. it is
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* *not* to provide linux compatibility.
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*/
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/* Trace the 3 different classes of read/write access to QBMan. #undef as
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* required. */
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#undef QBMAN_CCSR_TRACE
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#undef QBMAN_CINH_TRACE
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#undef QBMAN_CENA_TRACE
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/* Temporarily define this to get around the fact that cache enabled mapping is
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* not working right now. Will remove this after uboot could map the cache
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* enabled portal memory.
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*/
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#define QBMAN_CINH_ONLY
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static inline void word_copy(void *d, const void *s, unsigned int cnt)
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{
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uint32_t *dd = d;
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const uint32_t *ss = s;
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while (cnt--)
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*(dd++) = *(ss++);
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}
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/* Currently, the CENA support code expects each 32-bit word to be written in
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* host order, and these are converted to hardware (little-endian) order on
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* command submission. However, 64-bit quantities are must be written (and read)
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* as two 32-bit words with the least-significant word first, irrespective of
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* host endianness. */
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static inline void u64_to_le32_copy(void *d, const uint64_t *s,
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unsigned int cnt)
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{
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uint32_t *dd = d;
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const uint32_t *ss = (const uint32_t *)s;
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while (cnt--) {
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/* TBD: the toolchain was choking on the use of 64-bit types up
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* until recently so this works entirely with 32-bit variables.
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* When 64-bit types become usable again, investigate better
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* ways of doing this. */
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#if defined(__BIG_ENDIAN)
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*(dd++) = ss[1];
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*(dd++) = ss[0];
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ss += 2;
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#else
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*(dd++) = *(ss++);
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*(dd++) = *(ss++);
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#endif
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}
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}
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static inline void u64_from_le32_copy(uint64_t *d, const void *s,
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unsigned int cnt)
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{
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const uint32_t *ss = s;
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uint32_t *dd = (uint32_t *)d;
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while (cnt--) {
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#if defined(__BIG_ENDIAN)
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dd[1] = *(ss++);
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dd[0] = *(ss++);
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dd += 2;
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#else
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*(dd++) = *(ss++);
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*(dd++) = *(ss++);
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#endif
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}
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}
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/* Convert a host-native 32bit value into little endian */
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#if defined(__BIG_ENDIAN)
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static inline uint32_t make_le32(uint32_t val)
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{
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return ((val & 0xff) << 24) | ((val & 0xff00) << 8) |
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((val & 0xff0000) >> 8) | ((val & 0xff000000) >> 24);
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}
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#else
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#define make_le32(val) (val)
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#endif
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static inline void make_le32_n(uint32_t *val, unsigned int num)
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{
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while (num--) {
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*val = make_le32(*val);
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val++;
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}
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}
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/******************/
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/* Portal access */
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/******************/
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struct qbman_swp_sys {
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/* On GPP, the sys support for qbman_swp is here. The CENA region isi
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* not an mmap() of the real portal registers, but an allocated
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* place-holder, because the actual writes/reads to/from the portal are
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* marshalled from these allocated areas using QBMan's "MC access
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* registers". CINH accesses are atomic so there's no need for a
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* place-holder. */
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void *cena;
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void __iomem *addr_cena;
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void __iomem *addr_cinh;
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};
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/* P_OFFSET is (ACCESS_CMD,0,12) - offset within the portal
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* C is (ACCESS_CMD,12,1) - is inhibited? (0==CENA, 1==CINH)
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* SWP_IDX is (ACCESS_CMD,16,10) - Software portal index
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* P is (ACCESS_CMD,28,1) - (0==special portal, 1==any portal)
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* T is (ACCESS_CMD,29,1) - Command type (0==READ, 1==WRITE)
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* E is (ACCESS_CMD,31,1) - Command execute (1 to issue, poll for 0==complete)
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*/
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static inline void qbman_cinh_write(struct qbman_swp_sys *s, uint32_t offset,
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uint32_t val)
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{
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__raw_writel(val, s->addr_cinh + offset);
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#ifdef QBMAN_CINH_TRACE
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pr_info("qbman_cinh_write(%p:0x%03x) 0x%08x\n",
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s->addr_cinh, offset, val);
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#endif
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}
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static inline uint32_t qbman_cinh_read(struct qbman_swp_sys *s, uint32_t offset)
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{
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uint32_t reg = __raw_readl(s->addr_cinh + offset);
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#ifdef QBMAN_CINH_TRACE
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pr_info("qbman_cinh_read(%p:0x%03x) 0x%08x\n",
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s->addr_cinh, offset, reg);
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#endif
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return reg;
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}
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static inline void *qbman_cena_write_start(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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void *shadow = s->cena + offset;
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#ifdef QBMAN_CENA_TRACE
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pr_info("qbman_cena_write_start(%p:0x%03x) %p\n",
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s->addr_cena, offset, shadow);
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#endif
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BUG_ON(offset & 63);
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dcbz(shadow);
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return shadow;
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}
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static inline void qbman_cena_write_complete(struct qbman_swp_sys *s,
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uint32_t offset, void *cmd)
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{
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const uint32_t *shadow = cmd;
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int loop;
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#ifdef QBMAN_CENA_TRACE
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pr_info("qbman_cena_write_complete(%p:0x%03x) %p\n",
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s->addr_cena, offset, shadow);
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hexdump(cmd, 64);
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#endif
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for (loop = 15; loop >= 0; loop--)
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#ifdef QBMAN_CINH_ONLY
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__raw_writel(shadow[loop], s->addr_cinh +
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offset + loop * 4);
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#else
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__raw_writel(shadow[loop], s->addr_cena +
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offset + loop * 4);
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#endif
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}
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static inline void *qbman_cena_read(struct qbman_swp_sys *s, uint32_t offset)
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{
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uint32_t *shadow = s->cena + offset;
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unsigned int loop;
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#ifdef QBMAN_CENA_TRACE
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pr_info("qbman_cena_read(%p:0x%03x) %p\n",
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s->addr_cena, offset, shadow);
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#endif
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for (loop = 0; loop < 16; loop++)
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#ifdef QBMAN_CINH_ONLY
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shadow[loop] = __raw_readl(s->addr_cinh + offset
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+ loop * 4);
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#else
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shadow[loop] = __raw_readl(s->addr_cena + offset
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+ loop * 4);
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#endif
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#ifdef QBMAN_CENA_TRACE
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hexdump(shadow, 64);
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#endif
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return shadow;
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}
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static inline void qbman_cena_invalidate_prefetch(struct qbman_swp_sys *s,
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uint32_t offset)
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{
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}
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/******************/
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/* Portal support */
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/******************/
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/* The SWP_CFG portal register is special, in that it is used by the
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* platform-specific code rather than the platform-independent code in
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* qbman_portal.c. So use of it is declared locally here. */
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#define QBMAN_CINH_SWP_CFG 0xd00
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/* For MC portal use, we always configure with
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* DQRR_MF is (SWP_CFG,20,3) - DQRR max fill (<- 0x4)
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* EST is (SWP_CFG,16,3) - EQCR_CI stashing threshold (<- 0x0)
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* RPM is (SWP_CFG,12,2) - RCR production notification mode (<- 0x3)
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* DCM is (SWP_CFG,10,2) - DQRR consumption notification mode (<- 0x2)
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* EPM is (SWP_CFG,8,2) - EQCR production notification mode (<- 0x3)
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* SD is (SWP_CFG,5,1) - memory stashing drop enable (<- FALSE)
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* SP is (SWP_CFG,4,1) - memory stashing priority (<- TRUE)
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* SE is (SWP_CFG,3,1) - memory stashing enable (<- 0x0)
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* DP is (SWP_CFG,2,1) - dequeue stashing priority (<- TRUE)
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* DE is (SWP_CFG,1,1) - dequeue stashing enable (<- 0x0)
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* EP is (SWP_CFG,0,1) - EQCR_CI stashing priority (<- FALSE)
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*/
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static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn,
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uint8_t est, uint8_t rpm, uint8_t dcm,
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uint8_t epm, int sd, int sp, int se,
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int dp, int de, int ep)
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{
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uint32_t reg;
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reg = e32_uint8_t(20, 3, max_fill) | e32_uint8_t(16, 3, est) |
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e32_uint8_t(12, 2, rpm) | e32_uint8_t(10, 2, dcm) |
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e32_uint8_t(8, 2, epm) | e32_int(5, 1, sd) |
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e32_int(4, 1, sp) | e32_int(3, 1, se) | e32_int(2, 1, dp) |
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e32_int(1, 1, de) | e32_int(0, 1, ep) | e32_uint8_t(14, 1, wn);
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return reg;
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}
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static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,
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const struct qbman_swp_desc *d)
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{
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uint32_t reg;
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s->addr_cena = d->cena_bar;
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s->addr_cinh = d->cinh_bar;
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s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE);
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memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE);
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if (!s->cena) {
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printf("Could not allocate page for cena shadow\n");
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return -1;
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}
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#ifdef QBMAN_CHECKING
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/* We should never be asked to initialise for a portal that isn't in
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* the power-on state. (Ie. don't forget to reset portals when they are
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* decommissioned!)
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*/
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reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
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BUG_ON(reg);
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#endif
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#ifdef QBMAN_CINH_ONLY
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reg = qbman_set_swp_cfg(4, 1, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
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#else
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reg = qbman_set_swp_cfg(4, 0, 0, 3, 2, 3, 0, 1, 0, 1, 0, 0);
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#endif
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qbman_cinh_write(s, QBMAN_CINH_SWP_CFG, reg);
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reg = qbman_cinh_read(s, QBMAN_CINH_SWP_CFG);
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if (!reg) {
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printf("The portal is not enabled!\n");
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free(s->cena);
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return -1;
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}
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return 0;
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}
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static inline void qbman_swp_sys_finish(struct qbman_swp_sys *s)
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{
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free((void *)s->cena);
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}
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