234 lines
		
	
	
		
			6.4 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			234 lines
		
	
	
		
			6.4 KiB
		
	
	
	
		
			C
		
	
	
	
/*
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 * Copyright (C) ST-Ericsson SA 2009
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 *
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 * SPDX-License-Identifier:	GPL-2.0+
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 */
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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 * #define DEBUG 1
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 */
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SNOWBALL
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_BOARD_LATE_INIT
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/*
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 * High Level Configuration Options
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 * (easy to change)
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 */
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#define CONFIG_U8500
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#define CONFIG_SYS_MEMTEST_START	0x00000000
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#define CONFIG_SYS_MEMTEST_END	0x1FFFFFFF
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/*-----------------------------------------------------------------------
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 * Size of environment and malloc() pool
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 */
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/*
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 * If you use U-Boot as crash kernel, make sure that it does not overwrite
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 * information saved by kexec during panic. Kexec expects the start
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 * address of the executable 32K above "crashkernel" address.
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 */
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/*
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 * Size of malloc() pool
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 */
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#define CONFIG_ENV_SIZE		(8*1024)
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#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 256*1024)
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_CMD_ENV
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#define CONFIG_ENV_OFFSET		0x0118000
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#define CONFIG_SYS_MMC_ENV_DEV          0              /* SLOT2: eMMC */
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/*
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 * PL011 Configuration
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 */
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#define CONFIG_PL011_SERIAL
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#define CONFIG_PL011_SERIAL_RLCR
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#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
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/*
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 * U8500 UART registers base for 3 serial devices
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 */
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#define CFG_UART0_BASE		0x80120000
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#define CFG_UART1_BASE		0x80121000
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#define CFG_UART2_BASE		0x80007000
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#define CFG_SERIAL0		CFG_UART0_BASE
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#define CFG_SERIAL1		CFG_UART1_BASE
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#define CFG_SERIAL2		CFG_UART2_BASE
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#define CONFIG_PL011_CLOCK	38400000
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#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
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				  (void *)CFG_SERIAL2 }
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#define CONFIG_CONS_INDEX	2
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#define CONFIG_BAUDRATE		115200
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/*
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 * Devices and file systems
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 */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DOS_PARTITION
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/*
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 * Commands
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 */
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#ifndef CONFIG_BOOTDELAY
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#define CONFIG_BOOTDELAY	1
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#endif
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#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"mmc dev 1; "								\
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	"if run loadbootscript; "					\
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		"then run bootscript; "					\
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	"else "								\
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		"if run mmcload; "					\
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			"then run mmcboot; "				\
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		"else "							\
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			"mmc dev 0; "					\
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			"if run emmcloadbootscript; "			\
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				"then run bootscript; "			\
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			"else "						\
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				"if run emmcload; "			\
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					"then run emmcboot; "		\
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				"else "					\
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					"echo No media to boot from; "	\
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				"fi; "					\
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			"fi; "						\
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		"fi; "							\
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	"fi; "
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#define CONFIG_EXTRA_ENV_SETTINGS \
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	"verify=n\0"							\
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	"loadaddr=0x00100000\0"						\
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	"console=ttyAMA2,115200n8\0"					\
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	"loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0"		\
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	"emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0"	\
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	"bootscript=echo Running bootscript "				\
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		"from mmc ...; source ${loadaddr}\0"			\
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	"memargs256=mem=96M@0 mem_modem=32M@96M mem=32M@128M "		\
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		"hwmem=22M@160M pmem_hwb=42M@182M mem_mali=32@224M\0"	\
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	"memargs512=mem=96M@0 mem_modem=32M@96M hwmem=32M@128M "	\
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		"mem=64M@160M mem_mali=32M@224M "			\
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		"pmem_hwb=128M@256M mem=128M@384M\0"			\
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	"memargs1024=mem=128M@0 mali.mali_mem=32M@128M "		\
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		"hwmem=168M@M160M mem=48M@328M "			\
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		"mem_issw=1M@383M mem=640M@384M\0"			\
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	"memargs=setenv bootargs ${bootargs} ${memargs1024}\0"		\
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	"emmcload=fatload mmc 0:2 ${loadaddr} uImage\0"			\
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	"mmcload=fatload mmc 1:1 ${loadaddr} uImage\0"			\
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	"commonargs=setenv bootargs console=${console} "		\
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	"vmalloc=300M\0"						\
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	"emmcargs=setenv bootargs ${bootargs} "				\
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		"root=/dev/mmcblk0p3 "					\
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		"rootwait\0"						\
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	"addcons=setenv bootargs ${bootargs} "				\
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		"console=${console}\0"					\
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	"emmcboot=echo Booting from eMMC ...; "				\
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		"run commonargs emmcargs memargs; "			\
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		"bootm ${loadaddr}\0"					\
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	"mmcargs=setenv bootargs ${bootargs} "				\
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		"root=/dev/mmcblk1p2 "					\
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		"rootwait earlyprintk\0"				\
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	"mmcboot=echo Booting from external MMC ...; "			\
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		"run commonargs mmcargs memargs; "			\
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		"bootm ${loadaddr}\0"					\
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	"fdt_high=0x2BC00000\0"						\
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	"stdout=serial,usbtty\0"					\
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	"stdin=serial,usbtty\0"						\
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	"stderr=serial,usbtty\0"
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/*-----------------------------------------------------------------------
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 * Miscellaneous configurable options
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 */
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#define CONFIG_SYS_LONGHELP			/* undef to save memory     */
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#define CONFIG_SYS_PROMPT	"U8500 $ "	/* Monitor Command Prompt   */
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#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
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					+ sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
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#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR		0x00100000 /* default load address */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
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#define CONFIG_SYS_HUSH_PARSER		1
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SETUP_MEMORY_TAGS	2
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#define CONFIG_INITRD_TAG		1
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#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
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/*
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 * Physical Memory Map
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 */
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#define CONFIG_NR_DRAM_BANKS		1
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#define PHYS_SDRAM_1			0x00000000	/* DDR-SDRAM Bank #1 */
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/*
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 * additions for new relocation code
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 */
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#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
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#define CONFIG_SYS_MAX_RAM_SIZE	0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE	0x100000
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#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
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					 CONFIG_SYS_INIT_RAM_SIZE - \
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					 GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
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/* landing address before relocation */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE            0x0
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#endif
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/*
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 * MMC related configs
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 */
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#define CONFIG_ARM_PL180_MMCI
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#define MMC_BLOCK_SIZE			512
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#define CFG_EMMC_BASE                   0x80114000
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#define CFG_MMC_BASE                    0x80126000
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/*
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 * FLASH and environment organization
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 */
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#define CONFIG_SYS_NO_FLASH
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/*
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 * base register values for U8500
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 */
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#define CFG_PRCMU_BASE		0x80157000	/* Power, reset and clock */
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/*
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 * U8500 GPIO register base for 9 banks
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 */
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#define CONFIG_DB8500_GPIO
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#define CFG_GPIO_0_BASE			0x8012E000
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#define CFG_GPIO_1_BASE			0x8012E080
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#define CFG_GPIO_2_BASE			0x8000E000
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#define CFG_GPIO_3_BASE			0x8000E080
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#define CFG_GPIO_4_BASE			0x8000E100
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#define CFG_GPIO_5_BASE			0x8000E180
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#define CFG_GPIO_6_BASE			0x8011E000
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#define CFG_GPIO_7_BASE			0x8011E080
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#define CFG_GPIO_8_BASE			0xA03FE000
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#define CFG_FSMC_BASE		0x80000000	/* FSMC Controller */
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#endif	/* __CONFIG_H */
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