260 lines
6.8 KiB
C
260 lines
6.8 KiB
C
/*
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* (C) Copyright 2007
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* Developed for DENX Software Engineering GmbH.
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*
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* Author: Pavel Kolesnikov <concord@emcraft.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* define DEBUG for debugging output (obviously ;-)) */
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <watchdog.h>
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_ECC
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/*
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* MEMORY ECC test
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*
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* This test performs the checks ECC facility of memory.
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*/
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <asm/ppc440.h>
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DECLARE_GLOBAL_DATA_PTR;
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const static uint8_t syndrome_codes[] = {
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0xF4, 0XF1, 0XEC, 0XEA, 0XE9, 0XE6, 0XE5, 0XE3,
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0XDC, 0XDA, 0XD9, 0XD6, 0XD5, 0XD3, 0XCE, 0XCB,
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0xB5, 0XB0, 0XAD, 0XAB, 0XA8, 0XA7, 0XA4, 0XA2,
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0X9D, 0X9B, 0X98, 0X97, 0X94, 0X92, 0X8F, 0X8A,
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0x75, 0x70, 0X6D, 0X6B, 0X68, 0X67, 0X64, 0X62,
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0X5E, 0X5B, 0X58, 0X57, 0X54, 0X52, 0X4F, 0X4A,
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0x34, 0x31, 0X2C, 0X2A, 0X29, 0X26, 0X25, 0X23,
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0X1C, 0X1A, 0X19, 0X16, 0X15, 0X13, 0X0E, 0X0B,
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0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
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};
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#define ECC_START_ADDR 0x10
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#define ECC_STOP_ADDR 0x2000
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#define ECC_PATTERN 0x01010101
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#define ECC_PATTERN_CORR 0x11010101
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#define ECC_PATTERN_UNCORR 0x61010101
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inline static void disable_ecc(void)
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{
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uint32_t value;
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sync(); /* Wait for any pending memory accesses to complete. */
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_DISABLE);
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}
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inline static void clear_and_enable_ecc(void)
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{
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uint32_t value;
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sync(); /* Wait for any pending memory accesses to complete. */
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mfsdram(DDR0_00, value);
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mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
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mfsdram(DDR0_22, value);
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mtsdram(DDR0_22, (value & ~DDR0_22_CTRL_RAW_MASK)
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| DDR0_22_CTRL_RAW_ECC_ENABLE);
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}
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static uint32_t get_ecc_status(void)
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{
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uint32_t int_status;
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#if defined(DEBUG)
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uint8_t syndrome;
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uint32_t hdata, ldata, haddr, laddr;
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uint32_t value;
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#endif
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mfsdram(DDR0_00, int_status);
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int_status &= DDR0_00_INT_STATUS_MASK;
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#if defined(DEBUG)
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if (int_status & (DDR0_00_INT_STATUS_BIT0 | DDR0_00_INT_STATUS_BIT1)) {
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mfsdram(DDR0_32, laddr);
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mfsdram(DDR0_33, haddr);
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haddr &= 0x00000001;
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if (int_status & DDR0_00_INT_STATUS_BIT1)
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debug("Multiple accesses");
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else
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debug("A single access");
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debug(" outside the defined physical memory space detected\n"
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" addr = 0x%01x%08x\n", haddr, laddr);
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}
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if (int_status & (DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT3)) {
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unsigned int bit;
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mfsdram(DDR0_23, value);
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syndrome = (value >> 16) & 0xff;
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for (bit = 0; bit < sizeof(syndrome_codes); bit++)
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if (syndrome_codes[bit] == syndrome)
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break;
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mfsdram(DDR0_38, laddr);
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mfsdram(DDR0_39, haddr);
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haddr &= 0x00000001;
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mfsdram(DDR0_40, ldata);
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mfsdram(DDR0_41, hdata);
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if (int_status & DDR0_00_INT_STATUS_BIT3)
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debug("Multiple correctable ECC events");
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else
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debug("Single correctable ECC event");
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debug(" detected\n 0x%01x%08x - 0x%08x%08x, bit - %d\n",
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haddr, laddr, hdata, ldata, bit);
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}
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if (int_status & (DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT5)) {
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mfsdram(DDR0_23, value);
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syndrome = (value >> 8) & 0xff;
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mfsdram(DDR0_34, laddr);
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mfsdram(DDR0_35, haddr);
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haddr &= 0x00000001;
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mfsdram(DDR0_36, ldata);
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mfsdram(DDR0_37, hdata);
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if (int_status & DDR0_00_INT_STATUS_BIT5)
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debug("Multiple uncorrectable ECC events");
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else
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debug("Single uncorrectable ECC event");
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debug(" detected\n 0x%01x%08x - 0x%08x%08x, "
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"syndrome - 0x%02x\n",
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haddr, laddr, hdata, ldata, syndrome);
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}
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if (int_status & DDR0_00_INT_STATUS_BIT6)
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debug("DRAM initialization complete\n");
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#endif /* defined(DEBUG) */
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return int_status;
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}
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static int test_ecc(uint32_t ecc_addr)
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{
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uint32_t value;
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volatile uint32_t *const ecc_mem = (volatile uint32_t *)ecc_addr;
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int ret = 0;
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WATCHDOG_RESET();
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debug("Entering test_ecc(0x%08x)\n", ecc_addr);
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/* Set up correct ECC in memory */
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disable_ecc();
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clear_and_enable_ecc();
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out_be32(ecc_mem, ECC_PATTERN);
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out_be32(ecc_mem + 1, ECC_PATTERN);
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ppcDcbf((u32)ecc_mem);
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/* Verify no ECC error reading back */
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value = in_be32(ecc_mem);
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disable_ecc();
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if (ECC_PATTERN != value) {
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debug("Data read error (no-error case): "
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"expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
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ret = 1;
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}
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value = get_ecc_status();
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if (0x00000000 != value) {
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/* Expected no ECC status reported */
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debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
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0x00000000, value);
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ret = 1;
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}
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/* Test for correctable error by creating a one-bit error */
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out_be32(ecc_mem, ECC_PATTERN_CORR);
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ppcDcbf((u32)ecc_mem);
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clear_and_enable_ecc();
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value = in_be32(ecc_mem);
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disable_ecc();
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/* Test that the corrected data was read */
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if (ECC_PATTERN != value) {
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debug("Data read error (correctable-error case): "
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"expected 0x%08x, read 0x%08x\n", ECC_PATTERN, value);
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ret = 1;
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}
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value = get_ecc_status();
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if ((DDR0_00_INT_STATUS_BIT2 | DDR0_00_INT_STATUS_BIT7) != value) {
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/* Expected a single correctable error reported */
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debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
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DDR0_00_INT_STATUS_BIT2, value);
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ret = 1;
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}
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/* Test for uncorrectable error by creating a two-bit error */
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out_be32(ecc_mem, ECC_PATTERN_UNCORR);
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ppcDcbf((u32)ecc_mem);
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clear_and_enable_ecc();
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value = in_be32(ecc_mem);
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disable_ecc();
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/* Test that the corrected data was read */
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if (ECC_PATTERN_UNCORR != value) {
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debug("Data read error (uncorrectable-error case): "
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"expected 0x%08x, read 0x%08x\n", ECC_PATTERN_UNCORR,
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value);
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ret = 1;
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}
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value = get_ecc_status();
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if ((DDR0_00_INT_STATUS_BIT4 | DDR0_00_INT_STATUS_BIT7) != value) {
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/* Expected a single uncorrectable error reported */
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debug("get_ecc_status(): expected 0x%08x, got 0x%08x\n",
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DDR0_00_INT_STATUS_BIT4, value);
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ret = 1;
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}
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/* Remove error from SDRAM and enable ECC. */
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out_be32(ecc_mem, ECC_PATTERN);
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ppcDcbf((u32)ecc_mem);
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clear_and_enable_ecc();
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return ret;
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}
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int ecc_post_test(int flags)
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{
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int ret = 0;
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uint32_t value;
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uint32_t iaddr;
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mfsdram(DDR0_22, value);
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if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) {
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debug("SDRAM ECC not enabled, skipping ECC POST.\n");
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return 0;
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}
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/* Mask all interrupts. */
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mfsdram(DDR0_01, value);
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mtsdram(DDR0_01, (value & ~DDR0_01_INT_MASK_MASK)
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| DDR0_01_INT_MASK_ALL_OFF);
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for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) {
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ret = test_ecc(iaddr);
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if (ret)
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break;
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}
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/*
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* Clear possible errors resulting from ECC testing. (If not done, we
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* we could get an interrupt later on when exceptions are enabled.)
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*/
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set_mcsr(get_mcsr());
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debug("ecc_post_test() returning %d\n", ret);
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return ret;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_ECC */
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#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
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