290 lines
7.7 KiB
C
290 lines
7.7 KiB
C
/*
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/ic/sc520.h>
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#include <net.h>
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#include <netdev.h>
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#ifdef CONFIG_HW_WATCHDOG
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#include <watchdog.h>
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#endif
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#include "hardware.h"
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DECLARE_GLOBAL_DATA_PTR;
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unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
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static void enet_timer_isr(void);
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static void enet_toggle_run_led(void);
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static void enet_setup_pars(void);
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/*
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* Miscellaneous platform dependent initializations
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*/
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int board_early_init_f(void)
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{
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u16 pio_out_cfg = 0x0000;
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/* Configure General Purpose Bus timing */
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writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
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writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
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writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
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writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
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writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
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writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
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writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
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/* Configure Programmable Input/Output Pins */
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writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
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writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
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writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
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writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
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writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
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writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
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/*
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* Turn off top board
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* Set StrataFlash chips to 16-bit width
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* Set StrataFlash chips to normal (non reset/power down) mode
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*/
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pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
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pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
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pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
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pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
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writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
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/* Turn off auxiliary power output */
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writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
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/* Clear FPGA program mode */
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writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
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enet_setup_pars();
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/* Disable Watchdog */
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writew(0x3333, &sc520_mmcr->wdtmrctl);
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writew(0xcccc, &sc520_mmcr->wdtmrctl);
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writew(0x0000, &sc520_mmcr->wdtmrctl);
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/* Chip Select Configuration */
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writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
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writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
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writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
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writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
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writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
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writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
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writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
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writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
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/* enable posted-writes */
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writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
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return 0;
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}
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static void enet_setup_pars(void)
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{
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/*
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* PARs 11 and 12 are 2MB SRAM @ 0x19000000
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*
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* These are setup now because older version of U-Boot have them
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* mapped to a different PAR which gets clobbered which prevents
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* using SRAM for warm-booting a new image
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*/
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writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
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writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
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/* PARs 0 and 1 are Compact Flash slots (4kB each) */
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writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
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writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
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/* PAR 2 is used for Cache-As-RAM */
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/*
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* PARs 5 through 8 are additional NS16550 UARTS
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* 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
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*/
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writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
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writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
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writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
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writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
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/* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
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writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
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writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
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/* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
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writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
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/*
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* PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
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* Already configured in board_init16 (eNET_start16.S)
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*
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* PAR 15 is Boot ROM
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* Already configured in board_init16 (eNET_start16.S)
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*/
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}
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int board_early_init_r(void)
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{
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/* CPU Speed to 100MHz */
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gd->cpu_clk = 100000000;
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/* Crystal is 33.000MHz */
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gd->bus_clk = 33000000;
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return 0;
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}
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void show_boot_progress(int val)
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{
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uchar led_mask;
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led_mask = 0x00;
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if (val < 0)
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led_mask |= LED_ERR_BITMASK;
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led_mask |= (uchar)(val & 0x001f);
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outb(led_mask, LED_LATCH_ADDRESS);
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}
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int last_stage_init(void)
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{
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int minor;
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int major;
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major = minor = 0;
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outb(0x00, LED_LATCH_ADDRESS);
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register_timer_isr(enet_timer_isr);
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printf("Serck Controls eNET\n");
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return 0;
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}
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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if (banknum == 0) { /* non-CFI boot flash */
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info->portwidth = FLASH_CFI_8BIT;
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info->chipwidth = FLASH_CFI_BY8;
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info->interface = FLASH_CFI_X8;
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return 1;
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} else {
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return 0;
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}
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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void setup_pcat_compatibility()
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{
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/* disable global interrupt mode */
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writeb(0x40, &sc520_mmcr->picicr);
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/* set all irqs to edge */
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writeb(0x00, &sc520_mmcr->pic_mode[0]);
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writeb(0x00, &sc520_mmcr->pic_mode[1]);
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writeb(0x00, &sc520_mmcr->pic_mode[2]);
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/*
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* active low polarity on PIC interrupt pins,
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* active high polarity on all other irq pins
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*/
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writew(0x0000,&sc520_mmcr->intpinpol);
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/*
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* PIT 0 -> IRQ0
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* RTC -> IRQ8
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* FP error -> IRQ13
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* UART1 -> IRQ4
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* UART2 -> IRQ3
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*/
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writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
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writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
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writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
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writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
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writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
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/* Disable all other interrupt sources */
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
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writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
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}
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void enet_timer_isr(void)
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{
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static long enet_ticks = 0;
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enet_ticks++;
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/* Toggle Watchdog every 100ms */
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if ((enet_ticks % 100) == 0)
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hw_watchdog_reset();
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/* Toggle Run LED every 500ms */
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if ((enet_ticks % 500) == 0)
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enet_toggle_run_led();
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}
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void hw_watchdog_reset(void)
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{
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/* Watchdog Reset must be atomic */
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long flag = disable_interrupts();
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if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
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sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
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else
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sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
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if (flag)
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enable_interrupts();
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}
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void enet_toggle_run_led(void)
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{
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unsigned char leds_state= inb(LED_LATCH_ADDRESS);
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if (leds_state & LED_RUN_BITMASK)
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outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
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else
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outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
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}
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