121 lines
2.8 KiB
C
121 lines
2.8 KiB
C
/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_reset_manager *reset_manager_base =
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(void *)SOCFPGA_RSTMGR_ADDRESS;
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static struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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/* Assert or de-assert SoCFPGA reset manager reset. */
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void socfpga_per_reset(u32 reset, int set)
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{
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const void *reg;
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if (RSTMGR_BANK(reset) == 0)
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reg = &reset_manager_base->mpu_mod_reset;
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else if (RSTMGR_BANK(reset) == 1)
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reg = &reset_manager_base->per_mod_reset;
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else if (RSTMGR_BANK(reset) == 2)
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reg = &reset_manager_base->per2_mod_reset;
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else if (RSTMGR_BANK(reset) == 3)
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reg = &reset_manager_base->brg_mod_reset;
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else if (RSTMGR_BANK(reset) == 4)
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reg = &reset_manager_base->misc_mod_reset;
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else /* Invalid reset register, do nothing */
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return;
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if (set)
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setbits_le32(reg, 1 << RSTMGR_RESET(reset));
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else
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clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
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}
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/*
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* Assert reset on every peripheral but L4WD0.
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* Watchdog must be kept intact to prevent glitches
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* and/or hangs.
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*/
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void socfpga_per_reset_all(void)
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{
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const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
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writel(~l4wd0, &reset_manager_base->per_mod_reset);
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writel(0xffffffff, &reset_manager_base->per2_mod_reset);
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}
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/*
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* Write the reset manager register to cause reset
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*/
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void reset_cpu(ulong addr)
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{
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/* request a warm reset */
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writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
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&reset_manager_base->ctrl);
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/*
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* infinite loop here as watchdog will trigger and reset
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* the processor
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*/
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while (1)
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;
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}
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/*
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* Release peripherals from reset based on handoff
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*/
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void reset_deassert_peripherals_handoff(void)
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{
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writel(0, &reset_manager_base->per_mod_reset);
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}
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#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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void socfpga_bridges_reset(int enable)
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{
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/* For SoCFPGA-VT, this is NOP. */
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}
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#else
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#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
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#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
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#define L3REGS_REMAP_OCRAM_MASK 0x01
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void socfpga_bridges_reset(int enable)
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{
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const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
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L3REGS_REMAP_HPS2FPGA_MASK |
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L3REGS_REMAP_OCRAM_MASK;
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if (enable) {
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/* brdmodrst */
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writel(0xffffffff, &reset_manager_base->brg_mod_reset);
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} else {
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writel(0, &sysmgr_regs->iswgrp_handoff[0]);
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writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
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/* Check signal from FPGA. */
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if (!fpgamgr_test_fpga_ready()) {
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/* FPGA not ready, do nothing. */
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printf("%s: FPGA not ready, aborting.\n", __func__);
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return;
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}
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/* brdmodrst */
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writel(0, &reset_manager_base->brg_mod_reset);
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/* Remap the bridges into memory map */
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writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
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}
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}
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#endif
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