490 lines
9.9 KiB
C
490 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 NXP
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*/
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/delay.h>
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void ddrphy_coldreset(void)
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{
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/* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */
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/* dramphy_reset_n default 0 , assert -> 0, de_assert -> 1 */
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/* dramphy_PwrOKIn default 0 , assert -> 1, de_assert -> 0 */
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/* src_gen_dphy_apb_sw_rst_de_assert */
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clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
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/* src_gen_dphy_sw_rst_de_assert */
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clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
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/* src_gen_dphy_PwrOKIn_sw_rst_de_assert() */
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setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
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mdelay(10);
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/* src_gen_dphy_apb_sw_rst_assert */
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setbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
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/* src_gen_dphy_sw_rst_assert */
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setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
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mdelay(10);
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/* src_gen_dphy_PwrOKIn_sw_rst_assert */
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clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
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mdelay(10);
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/* src_gen_dphy_apb_sw_rst_de_assert */
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clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
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/* src_gen_dphy_sw_rst_de_assert() */
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clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
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}
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void check_ddrc_idle(void)
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{
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u32 regval;
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do {
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regval = readl(REG_DDRDSR_2);
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if (regval & BIT(31))
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break;
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} while (1);
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}
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void check_dfi_init_complete(void)
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{
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u32 regval;
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do {
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regval = readl(REG_DDRDSR_2);
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if (regval & BIT(2))
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break;
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} while (1);
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setbits_le32(REG_DDRDSR_2, BIT(2));
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}
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void ddrc_config(struct dram_cfg_param *ddrc_config, int num)
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{
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int i = 0;
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for (i = 0; i < num; i++) {
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writel(ddrc_config->val, (ulong)ddrc_config->reg);
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ddrc_config++;
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}
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}
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void get_trained_CDD(u32 fsp)
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{
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}
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int ddr_init(struct dram_timing_info *dram_timing)
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{
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unsigned int initial_drate;
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int ret;
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u32 regval;
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debug("DDRINFO: start DRAM init\n");
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/* reset ddrphy */
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ddrphy_coldreset();
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debug("DDRINFO: cfg clk\n");
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initial_drate = dram_timing->fsp_msg[0].drate;
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/* default to the frequency point 0 clock */
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ddrphy_init_set_dfi_clk(initial_drate);
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/*
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* Start PHY initialization and training by
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* accessing relevant PUB registers
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*/
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debug("DDRINFO:ddrphy config start\n");
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ret = ddr_cfg_phy(dram_timing);
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if (ret)
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return ret;
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debug("DDRINFO: ddrphy config done\n");
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/* rogram the ddrc registers */
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debug("DDRINFO: ddrc config start\n");
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ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
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debug("DDRINFO: ddrc config done\n");
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#ifdef CONFIG_IMX9_DRAM_PM_COUNTER
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writel(0x200000, REG_DDR_DEBUG_19);
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#endif
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check_dfi_init_complete();
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regval = readl(REG_DDR_SDRAM_CFG);
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writel((regval | 0x80000000), REG_DDR_SDRAM_CFG);
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check_ddrc_idle();
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/* save the dram timing config into memory */
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dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
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return 0;
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}
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ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr)
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{
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u32 paddr_apb_qual;
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u32 paddr_apb_unqual_dec_22_13;
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u32 paddr_apb_unqual_dec_19_13;
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u32 paddr_apb_unqual_dec_12_1;
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u32 paddr_apb_unqual;
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u32 paddr_apb_phy;
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paddr_apb_qual = (paddr_apb_from_ctlr << 1);
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paddr_apb_unqual_dec_22_13 = ((paddr_apb_qual & 0x7fe000) >> 13);
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paddr_apb_unqual_dec_12_1 = ((paddr_apb_qual & 0x1ffe) >> 1);
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switch (paddr_apb_unqual_dec_22_13) {
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case 0x000:
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paddr_apb_unqual_dec_19_13 = 0x00;
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break;
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case 0x001:
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paddr_apb_unqual_dec_19_13 = 0x01;
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break;
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case 0x002:
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paddr_apb_unqual_dec_19_13 = 0x02;
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break;
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case 0x003:
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paddr_apb_unqual_dec_19_13 = 0x03;
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break;
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case 0x004:
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paddr_apb_unqual_dec_19_13 = 0x04;
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break;
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case 0x005:
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paddr_apb_unqual_dec_19_13 = 0x05;
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break;
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case 0x006:
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paddr_apb_unqual_dec_19_13 = 0x06;
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break;
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case 0x007:
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paddr_apb_unqual_dec_19_13 = 0x07;
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break;
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case 0x008:
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paddr_apb_unqual_dec_19_13 = 0x08;
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break;
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case 0x009:
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paddr_apb_unqual_dec_19_13 = 0x09;
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break;
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case 0x00a:
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paddr_apb_unqual_dec_19_13 = 0x0a;
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break;
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case 0x00b:
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paddr_apb_unqual_dec_19_13 = 0x0b;
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break;
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case 0x100:
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paddr_apb_unqual_dec_19_13 = 0x0c;
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break;
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case 0x101:
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paddr_apb_unqual_dec_19_13 = 0x0d;
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break;
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case 0x102:
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paddr_apb_unqual_dec_19_13 = 0x0e;
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break;
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case 0x103:
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paddr_apb_unqual_dec_19_13 = 0x0f;
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break;
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case 0x104:
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paddr_apb_unqual_dec_19_13 = 0x10;
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break;
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case 0x105:
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paddr_apb_unqual_dec_19_13 = 0x11;
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break;
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case 0x106:
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paddr_apb_unqual_dec_19_13 = 0x12;
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break;
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case 0x107:
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paddr_apb_unqual_dec_19_13 = 0x13;
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break;
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case 0x108:
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paddr_apb_unqual_dec_19_13 = 0x14;
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break;
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case 0x109:
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paddr_apb_unqual_dec_19_13 = 0x15;
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break;
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case 0x10a:
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paddr_apb_unqual_dec_19_13 = 0x16;
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break;
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case 0x10b:
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paddr_apb_unqual_dec_19_13 = 0x17;
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break;
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case 0x200:
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paddr_apb_unqual_dec_19_13 = 0x18;
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break;
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case 0x201:
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paddr_apb_unqual_dec_19_13 = 0x19;
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break;
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case 0x202:
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paddr_apb_unqual_dec_19_13 = 0x1a;
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break;
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case 0x203:
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paddr_apb_unqual_dec_19_13 = 0x1b;
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break;
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case 0x204:
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paddr_apb_unqual_dec_19_13 = 0x1c;
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break;
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case 0x205:
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paddr_apb_unqual_dec_19_13 = 0x1d;
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break;
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case 0x206:
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paddr_apb_unqual_dec_19_13 = 0x1e;
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break;
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case 0x207:
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paddr_apb_unqual_dec_19_13 = 0x1f;
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break;
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case 0x208:
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paddr_apb_unqual_dec_19_13 = 0x20;
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break;
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case 0x209:
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paddr_apb_unqual_dec_19_13 = 0x21;
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break;
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case 0x20a:
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paddr_apb_unqual_dec_19_13 = 0x22;
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break;
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case 0x20b:
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paddr_apb_unqual_dec_19_13 = 0x23;
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break;
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case 0x300:
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paddr_apb_unqual_dec_19_13 = 0x24;
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break;
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case 0x301:
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paddr_apb_unqual_dec_19_13 = 0x25;
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break;
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case 0x302:
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paddr_apb_unqual_dec_19_13 = 0x26;
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break;
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case 0x303:
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paddr_apb_unqual_dec_19_13 = 0x27;
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break;
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case 0x304:
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paddr_apb_unqual_dec_19_13 = 0x28;
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break;
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case 0x305:
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paddr_apb_unqual_dec_19_13 = 0x29;
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break;
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case 0x306:
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paddr_apb_unqual_dec_19_13 = 0x2a;
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break;
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case 0x307:
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paddr_apb_unqual_dec_19_13 = 0x2b;
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break;
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case 0x308:
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paddr_apb_unqual_dec_19_13 = 0x2c;
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break;
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case 0x309:
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paddr_apb_unqual_dec_19_13 = 0x2d;
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break;
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case 0x30a:
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paddr_apb_unqual_dec_19_13 = 0x2e;
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break;
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case 0x30b:
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paddr_apb_unqual_dec_19_13 = 0x2f;
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break;
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case 0x010:
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paddr_apb_unqual_dec_19_13 = 0x30;
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break;
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case 0x011:
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paddr_apb_unqual_dec_19_13 = 0x31;
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break;
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case 0x012:
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paddr_apb_unqual_dec_19_13 = 0x32;
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break;
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case 0x013:
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paddr_apb_unqual_dec_19_13 = 0x33;
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break;
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case 0x014:
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paddr_apb_unqual_dec_19_13 = 0x34;
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break;
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case 0x015:
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paddr_apb_unqual_dec_19_13 = 0x35;
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break;
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case 0x016:
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paddr_apb_unqual_dec_19_13 = 0x36;
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break;
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case 0x017:
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paddr_apb_unqual_dec_19_13 = 0x37;
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break;
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case 0x018:
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paddr_apb_unqual_dec_19_13 = 0x38;
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break;
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case 0x019:
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paddr_apb_unqual_dec_19_13 = 0x39;
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break;
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case 0x110:
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paddr_apb_unqual_dec_19_13 = 0x3a;
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break;
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case 0x111:
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paddr_apb_unqual_dec_19_13 = 0x3b;
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break;
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case 0x112:
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paddr_apb_unqual_dec_19_13 = 0x3c;
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break;
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case 0x113:
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paddr_apb_unqual_dec_19_13 = 0x3d;
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break;
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case 0x114:
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paddr_apb_unqual_dec_19_13 = 0x3e;
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break;
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case 0x115:
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paddr_apb_unqual_dec_19_13 = 0x3f;
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break;
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case 0x116:
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paddr_apb_unqual_dec_19_13 = 0x40;
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break;
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case 0x117:
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paddr_apb_unqual_dec_19_13 = 0x41;
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break;
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case 0x118:
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paddr_apb_unqual_dec_19_13 = 0x42;
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break;
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case 0x119:
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paddr_apb_unqual_dec_19_13 = 0x43;
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break;
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case 0x210:
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paddr_apb_unqual_dec_19_13 = 0x44;
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break;
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case 0x211:
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paddr_apb_unqual_dec_19_13 = 0x45;
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break;
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case 0x212:
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paddr_apb_unqual_dec_19_13 = 0x46;
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break;
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case 0x213:
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paddr_apb_unqual_dec_19_13 = 0x47;
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break;
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case 0x214:
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paddr_apb_unqual_dec_19_13 = 0x48;
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break;
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case 0x215:
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paddr_apb_unqual_dec_19_13 = 0x49;
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break;
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case 0x216:
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paddr_apb_unqual_dec_19_13 = 0x4a;
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break;
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case 0x217:
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paddr_apb_unqual_dec_19_13 = 0x4b;
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break;
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case 0x218:
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paddr_apb_unqual_dec_19_13 = 0x4c;
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break;
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case 0x219:
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paddr_apb_unqual_dec_19_13 = 0x4d;
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break;
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case 0x310:
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paddr_apb_unqual_dec_19_13 = 0x4e;
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break;
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case 0x311:
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paddr_apb_unqual_dec_19_13 = 0x4f;
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break;
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case 0x312:
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paddr_apb_unqual_dec_19_13 = 0x50;
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break;
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case 0x313:
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paddr_apb_unqual_dec_19_13 = 0x51;
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break;
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case 0x314:
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paddr_apb_unqual_dec_19_13 = 0x52;
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break;
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case 0x315:
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paddr_apb_unqual_dec_19_13 = 0x53;
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break;
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case 0x316:
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paddr_apb_unqual_dec_19_13 = 0x54;
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break;
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case 0x317:
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paddr_apb_unqual_dec_19_13 = 0x55;
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break;
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case 0x318:
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paddr_apb_unqual_dec_19_13 = 0x56;
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break;
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case 0x319:
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paddr_apb_unqual_dec_19_13 = 0x57;
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break;
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case 0x020:
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paddr_apb_unqual_dec_19_13 = 0x58;
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break;
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case 0x120:
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paddr_apb_unqual_dec_19_13 = 0x59;
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break;
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case 0x220:
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paddr_apb_unqual_dec_19_13 = 0x5a;
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break;
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case 0x320:
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paddr_apb_unqual_dec_19_13 = 0x5b;
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break;
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case 0x040:
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paddr_apb_unqual_dec_19_13 = 0x5c;
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break;
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case 0x140:
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paddr_apb_unqual_dec_19_13 = 0x5d;
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break;
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case 0x240:
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paddr_apb_unqual_dec_19_13 = 0x5e;
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break;
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case 0x340:
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paddr_apb_unqual_dec_19_13 = 0x5f;
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break;
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case 0x050:
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paddr_apb_unqual_dec_19_13 = 0x60;
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break;
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case 0x051:
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paddr_apb_unqual_dec_19_13 = 0x61;
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break;
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case 0x052:
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paddr_apb_unqual_dec_19_13 = 0x62;
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break;
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case 0x053:
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paddr_apb_unqual_dec_19_13 = 0x63;
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break;
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case 0x054:
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paddr_apb_unqual_dec_19_13 = 0x64;
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break;
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case 0x055:
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paddr_apb_unqual_dec_19_13 = 0x65;
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break;
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case 0x056:
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paddr_apb_unqual_dec_19_13 = 0x66;
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break;
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case 0x057:
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paddr_apb_unqual_dec_19_13 = 0x67;
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break;
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case 0x070:
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paddr_apb_unqual_dec_19_13 = 0x68;
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break;
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case 0x090:
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paddr_apb_unqual_dec_19_13 = 0x69;
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break;
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case 0x190:
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paddr_apb_unqual_dec_19_13 = 0x6a;
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break;
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case 0x290:
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paddr_apb_unqual_dec_19_13 = 0x6b;
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break;
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case 0x390:
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paddr_apb_unqual_dec_19_13 = 0x6c;
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break;
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case 0x0c0:
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paddr_apb_unqual_dec_19_13 = 0x6d;
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break;
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case 0x0d0:
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paddr_apb_unqual_dec_19_13 = 0x6e;
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break;
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default:
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paddr_apb_unqual_dec_19_13 = 0x00;
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break;
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}
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paddr_apb_unqual = ((paddr_apb_unqual_dec_19_13 << 13) | (paddr_apb_unqual_dec_12_1 << 1));
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paddr_apb_phy = (paddr_apb_unqual << 1);
|
|
|
|
return paddr_apb_phy;
|
|
}
|