513 lines
16 KiB
C
513 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef __DDR3_AXP_H
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#define __DDR3_AXP_H
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#define MV_78XX0_Z1_REV 0x0
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#define MV_78XX0_A0_REV 0x1
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#define MV_78XX0_B0_REV 0x2
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#define SAR_DDR3_FREQ_MASK 0xFE00000
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#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
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#define MAX_CS 4
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#define MIN_DIMM_ADDR 0x50
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#define FAR_END_DIMM_ADDR 0x50
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#define MAX_DIMM_ADDR 0x60
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#ifndef CONFIG_DDR_FIXED_SIZE
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#define SDRAM_CS_SIZE 0xFFFFFFF
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#else
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#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1)
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#endif
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#define SDRAM_CS_BASE 0x0
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#define SDRAM_DIMM_SIZE 0x80000000
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#define CPU_CONFIGURATION_REG(id) (0x21800 + (id * 0x100))
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#define CPU_MRVL_ID_OFFSET 0x10
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#define SAR1_CPU_CORE_MASK 0x00000018
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#define SAR1_CPU_CORE_OFFSET 3
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/* Only enable ECC if the board selects it */
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#ifdef CONFIG_BOARD_ECC_SUPPORT
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#define ECC_SUPPORT
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#endif
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#define NEW_FABRIC_TWSI_ADDR 0x4E
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#ifdef CONFIG_DB_784MP_GP
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#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E
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#else
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#define BUS_WIDTH_ECC_TWSI_ADDR 0x4F
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#endif
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#define MV_MAX_DDR3_STATIC_SIZE 50
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#define MV_DDR3_MODES_NUMBER 30
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#define RESUME_RL_PATTERNS_ADDR (0xFE0000)
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#define RESUME_RL_PATTERNS_SIZE (0x100)
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#define RESUME_TRAINING_VALUES_ADDR (RESUME_RL_PATTERNS_ADDR + RESUME_RL_PATTERNS_SIZE)
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#define RESUME_TRAINING_VALUES_MAX (0xCD0)
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#define BOOT_INFO_ADDR (RESUME_RL_PATTERNS_ADDR + 0x1000)
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#define CHECKSUM_RESULT_ADDR (BOOT_INFO_ADDR + 0x1000)
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#define NUM_OF_REGISTER_ADDR (CHECKSUM_RESULT_ADDR + 4)
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#define SUSPEND_MAGIC_WORD (0xDEADB002)
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#define REGISTER_LIST_END (0xFFFFFFFF)
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/*
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* Registers offset
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*/
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#define REG_SAMPLE_RESET_LOW_ADDR 0x18230
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#define REG_SAMPLE_RESET_HIGH_ADDR 0x18234
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#define REG_SAMPLE_RESET_CPU_FREQ_OFFS 21
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#define REG_SAMPLE_RESET_CPU_FREQ_MASK 0x00E00000
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#define REG_SAMPLE_RESET_FAB_OFFS 24
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#define REG_SAMPLE_RESET_FAB_MASK 0xF000000
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#define REG_SAMPLE_RESET_TCLK_OFFS 28
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#define REG_SAMPLE_RESET_CPU_ARCH_OFFS 31
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#define REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS 20
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/* MISC */
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/*
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* In mainline U-Boot we're re-configuring the mvebu base address
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* register to 0xf1000000. So need to use this value for the DDR
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* training code as well.
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*/
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#define INTER_REGS_BASE SOC_REGS_PHY_BASE
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/* DDR */
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#define REG_SDRAM_CONFIG_ADDR 0x1400
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#define REG_SDRAM_CONFIG_MASK 0x9FFFFFFF
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#define REG_SDRAM_CONFIG_RFRS_MASK 0x3FFF
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#define REG_SDRAM_CONFIG_WIDTH_OFFS 15
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#define REG_SDRAM_CONFIG_REGDIMM_OFFS 17
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#define REG_SDRAM_CONFIG_ECC_OFFS 18
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#define REG_SDRAM_CONFIG_IERR_OFFS 19
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#define REG_SDRAM_CONFIG_PUPRSTDIV_OFFS 28
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#define REG_SDRAM_CONFIG_RSTRD_OFFS 30
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#define REG_DUNIT_CTRL_LOW_ADDR 0x1404
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#define REG_DUNIT_CTRL_LOW_2T_OFFS 3
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#define REG_DUNIT_CTRL_LOW_2T_MASK 0x3
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#define REG_DUNIT_CTRL_LOW_DPDE_OFFS 14
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#define REG_SDRAM_TIMING_LOW_ADDR 0x1408
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#define REG_SDRAM_TIMING_HIGH_ADDR 0x140C
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#define REG_SDRAM_TIMING_H_R2R_OFFS 7
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#define REG_SDRAM_TIMING_H_R2R_MASK 0x3
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#define REG_SDRAM_TIMING_H_R2W_W2R_OFFS 9
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#define REG_SDRAM_TIMING_H_R2W_W2R_MASK 0x3
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#define REG_SDRAM_TIMING_H_W2W_OFFS 11
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#define REG_SDRAM_TIMING_H_W2W_MASK 0x1F
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#define REG_SDRAM_TIMING_H_R2R_H_OFFS 19
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#define REG_SDRAM_TIMING_H_R2R_H_MASK 0x7
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#define REG_SDRAM_TIMING_H_R2W_W2R_H_OFFS 22
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#define REG_SDRAM_TIMING_H_R2W_W2R_H_MASK 0x7
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#define REG_SDRAM_ADDRESS_CTRL_ADDR 0x1410
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#define REG_SDRAM_ADDRESS_SIZE_OFFS 2
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#define REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS 18
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#define REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS 4
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#define REG_SDRAM_OPEN_PAGES_ADDR 0x1414
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#define REG_SDRAM_OPERATION_CS_OFFS 8
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#define REG_SDRAM_OPERATION_ADDR 0x1418
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#define REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS 24
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#define REG_SDRAM_OPERATION_CWA_DATA_OFFS 20
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#define REG_SDRAM_OPERATION_CWA_DATA_MASK 0xF
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#define REG_SDRAM_OPERATION_CWA_RC_OFFS 16
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#define REG_SDRAM_OPERATION_CWA_RC_MASK 0xF
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#define REG_SDRAM_OPERATION_CMD_MR0 0xF03
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#define REG_SDRAM_OPERATION_CMD_MR1 0xF04
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#define REG_SDRAM_OPERATION_CMD_MR2 0xF08
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#define REG_SDRAM_OPERATION_CMD_MR3 0xF09
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#define REG_SDRAM_OPERATION_CMD_RFRS 0xF02
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#define REG_SDRAM_OPERATION_CMD_CWA 0xF0E
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#define REG_SDRAM_OPERATION_CMD_RFRS_DONE 0xF
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#define REG_SDRAM_OPERATION_CMD_MASK 0xF
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#define REG_SDRAM_OPERATION_CS_OFFS 8
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#define REG_OUDDR3_TIMING_ADDR 0x142C
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#define REG_SDRAM_MODE_ADDR 0x141C
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#define REG_SDRAM_EXT_MODE_ADDR 0x1420
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#define REG_DDR_CONT_HIGH_ADDR 0x1424
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#define REG_ODT_TIME_LOW_ADDR 0x1428
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#define REG_ODT_ON_CTL_RD_OFFS 12
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#define REG_ODT_OFF_CTL_RD_OFFS 16
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#define REG_SDRAM_ERROR_ADDR 0x1454
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#define REG_SDRAM_AUTO_PWR_SAVE_ADDR 0x1474
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#define REG_ODT_TIME_HIGH_ADDR 0x147C
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#define REG_SDRAM_INIT_CTRL_ADDR 0x1480
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#define REG_SDRAM_INIT_CTRL_OFFS 0
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#define REG_SDRAM_INIT_CKE_ASSERT_OFFS 2
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#define REG_SDRAM_INIT_RESET_DEASSERT_OFFS 3
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#define REG_SDRAM_ODT_CTRL_LOW_ADDR 0x1494
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#define REG_SDRAM_ODT_CTRL_HIGH_ADDR 0x1498
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/*#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0xFFFFFF55 */
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#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_MASK 0x0
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#define REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA 0x3
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#define REG_DUNIT_ODT_CTRL_ADDR 0x149C
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#define REG_DUNIT_ODT_CTRL_OVRD_OFFS 8
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#define REG_DUNIT_ODT_CTRL_OVRD_VAL_OFFS 9
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#define REG_DRAM_FIFO_CTRL_ADDR 0x14A0
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#define REG_DRAM_AXI_CTRL_ADDR 0x14A8
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#define REG_DRAM_AXI_CTRL_AXIDATABUSWIDTH_OFFS 0
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#define REG_METAL_MASK_ADDR 0x14B0
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#define REG_METAL_MASK_MASK 0xDFFFFFFF
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#define REG_METAL_MASK_RETRY_OFFS 0
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#define REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR 0x14C0
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#define REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR 0x14C4
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#define REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR 0x14c8
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#define REG_DRAM_MAIN_PADS_CAL_ADDR 0x14CC
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#define REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR 0x17c8
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#define REG_CS_SIZE_SCRATCH_ADDR 0x1504
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#define REG_DYNAMIC_POWER_SAVE_ADDR 0x1520
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#define REG_DDR_IO_ADDR 0x1524
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#define REG_DDR_IO_CLK_RATIO_OFFS 15
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#define REG_DFS_ADDR 0x1528
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#define REG_DFS_DLLNEXTSTATE_OFFS 0
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#define REG_DFS_BLOCK_OFFS 1
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#define REG_DFS_SR_OFFS 2
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#define REG_DFS_ATSR_OFFS 3
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#define REG_DFS_RECONF_OFFS 4
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#define REG_DFS_CL_NEXT_STATE_OFFS 8
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#define REG_DFS_CL_NEXT_STATE_MASK 0xF
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#define REG_DFS_CWL_NEXT_STATE_OFFS 12
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#define REG_DFS_CWL_NEXT_STATE_MASK 0x7
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#define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538
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#define REG_READ_DATA_SAMPLE_DELAYS_MASK 0x1F
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#define REG_READ_DATA_SAMPLE_DELAYS_OFFS 8
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#define REG_READ_DATA_READY_DELAYS_ADDR 0x153C
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#define REG_READ_DATA_READY_DELAYS_MASK 0x1F
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#define REG_READ_DATA_READY_DELAYS_OFFS 8
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#define START_BURST_IN_ADDR 1
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#define REG_DRAM_TRAINING_SHADOW_ADDR 0x18488
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#define REG_DRAM_TRAINING_ADDR 0x15B0
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#define REG_DRAM_TRAINING_LOW_FREQ_OFFS 0
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#define REG_DRAM_TRAINING_PATTERNS_OFFS 4
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#define REG_DRAM_TRAINING_MED_FREQ_OFFS 2
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#define REG_DRAM_TRAINING_WL_OFFS 3
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#define REG_DRAM_TRAINING_RL_OFFS 6
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#define REG_DRAM_TRAINING_DQS_RX_OFFS 15
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#define REG_DRAM_TRAINING_DQS_TX_OFFS 16
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#define REG_DRAM_TRAINING_CS_OFFS 20
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#define REG_DRAM_TRAINING_RETEST_OFFS 24
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#define REG_DRAM_TRAINING_DFS_FREQ_OFFS 27
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#define REG_DRAM_TRAINING_DFS_REQ_OFFS 29
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#define REG_DRAM_TRAINING_ERROR_OFFS 30
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#define REG_DRAM_TRAINING_AUTO_OFFS 31
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#define REG_DRAM_TRAINING_RETEST_PAR 0x3
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#define REG_DRAM_TRAINING_RETEST_MASK 0xF8FFFFFF
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#define REG_DRAM_TRAINING_CS_MASK 0xFF0FFFFF
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#define REG_DRAM_TRAINING_PATTERNS_MASK 0xFF0F0000
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#define REG_DRAM_TRAINING_1_ADDR 0x15B4
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#define REG_DRAM_TRAINING_1_TRNBPOINT_OFFS 16
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#define REG_DRAM_TRAINING_2_ADDR 0x15B8
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#define REG_DRAM_TRAINING_2_OVERRUN_OFFS 17
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#define REG_DRAM_TRAINING_2_FIFO_RST_OFFS 4
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#define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3
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#define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2
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#define REG_DRAM_TRAINING_2_ECC_MUX_OFFS 1
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#define REG_DRAM_TRAINING_2_SW_OVRD_OFFS 0
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#define REG_DRAM_TRAINING_PATTERN_BASE_ADDR 0x15BC
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#define REG_DRAM_TRAINING_PATTERN_BASE_OFFS 3
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#define REG_TRAINING_DEBUG_2_ADDR 0x15C4
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#define REG_TRAINING_DEBUG_2_OFFS 16
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#define REG_TRAINING_DEBUG_2_MASK 0x3
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#define REG_TRAINING_DEBUG_3_ADDR 0x15C8
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#define REG_TRAINING_DEBUG_3_OFFS 3
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#define REG_TRAINING_DEBUG_3_MASK 0x7
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#define MR_CS_ADDR_OFFS 4
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#define REG_DDR3_MR0_ADDR 0x15D0
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#define REG_DDR3_MR0_CS_ADDR 0x1870
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#define REG_DDR3_MR0_CL_MASK 0x74
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#define REG_DDR3_MR0_CL_OFFS 2
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#define REG_DDR3_MR0_CL_HIGH_OFFS 3
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#define CL_MASK 0xF
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#define REG_DDR3_MR1_ADDR 0x15D4
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#define REG_DDR3_MR1_CS_ADDR 0x1874
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#define REG_DDR3_MR1_RTT_MASK 0xFFFFFDBB
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#define REG_DDR3_MR1_DLL_ENA_OFFS 0
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#define REG_DDR3_MR1_RTT_DISABLED 0x0
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#define REG_DDR3_MR1_RTT_RZQ2 0x40
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#define REG_DDR3_MR1_RTT_RZQ4 0x2
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#define REG_DDR3_MR1_RTT_RZQ6 0x42
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#define REG_DDR3_MR1_RTT_RZQ8 0x202
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#define REG_DDR3_MR1_RTT_RZQ12 0x4
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#define REG_DDR3_MR1_OUTBUF_WL_MASK 0xFFFFEF7F /* WL-disabled,OB-enabled */
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#define REG_DDR3_MR1_OUTBUF_DIS_OFFS 12 /* Output Buffer Disabled */
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#define REG_DDR3_MR1_WL_ENA_OFFS 7
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#define REG_DDR3_MR1_WL_ENA 0x80 /* WL Enabled */
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#define REG_DDR3_MR1_ODT_MASK 0xFFFFFDBB
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#define REG_DDR3_MR2_ADDR 0x15D8
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#define REG_DDR3_MR2_CS_ADDR 0x1878
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#define REG_DDR3_MR2_CWL_OFFS 3
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#define REG_DDR3_MR2_CWL_MASK 0x7
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#define REG_DDR3_MR2_ODT_MASK 0xFFFFF9FF
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#define REG_DDR3_MR3_ADDR 0x15DC
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#define REG_DDR3_MR3_CS_ADDR 0x187C
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#define REG_DDR3_RANK_CTRL_ADDR 0x15E0
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#define REG_DDR3_RANK_CTRL_CS_ENA_MASK 0xF
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#define REG_DDR3_RANK_CTRL_MIRROR_OFFS 4
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#define REG_ZQC_CONF_ADDR 0x15E4
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#define REG_DRAM_PHY_CONFIG_ADDR 0x15EC
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#define REG_DRAM_PHY_CONFIG_MASK 0x3FFFFFFF
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#define REG_ODPG_CNTRL_ADDR 0x1600
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#define REG_ODPG_CNTRL_OFFS 21
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#define REG_PHY_LOCK_MASK_ADDR 0x1670
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#define REG_PHY_LOCK_MASK_MASK 0xFFFFF000
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#define REG_PHY_LOCK_STATUS_ADDR 0x1674
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#define REG_PHY_LOCK_STATUS_LOCK_OFFS 9
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#define REG_PHY_LOCK_STATUS_LOCK_MASK 0xFFF
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#define REG_PHY_LOCK_APLL_ADLL_STATUS_MASK 0x7FF
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#define REG_PHY_REGISTRY_FILE_ACCESS_ADDR 0x16A0
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#define REG_PHY_REGISTRY_FILE_ACCESS_OP_WR 0xC0000000
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#define REG_PHY_REGISTRY_FILE_ACCESS_OP_RD 0x80000000
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#define REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE 0x80000000
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#define REG_PHY_BC_OFFS 27
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#define REG_PHY_CNTRL_OFFS 26
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#define REG_PHY_CS_OFFS 16
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#define REG_PHY_DQS_REF_DLY_OFFS 10
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#define REG_PHY_PHASE_OFFS 8
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#define REG_PHY_PUP_OFFS 22
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#define REG_TRAINING_WL_ADDR 0x16AC
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#define REG_TRAINING_WL_CS_MASK 0xFFFFFFFC
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#define REG_TRAINING_WL_UPD_OFFS 2
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#define REG_TRAINING_WL_CS_DONE_OFFS 3
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#define REG_TRAINING_WL_RATIO_MASK 0xFFFFFF0F
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#define REG_TRAINING_WL_1TO1 0x50
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#define REG_TRAINING_WL_2TO1 0x10
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#define REG_TRAINING_WL_DELAYEXP_MASK 0x20000000
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#define REG_TRAINING_WL_RESULTS_MASK 0x000001FF
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#define REG_TRAINING_WL_RESULTS_OFFS 20
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#define REG_REGISTERED_DRAM_CTRL_ADDR 0x16D0
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#define REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS 15
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#define REG_REGISTERED_DRAM_CTRL_PARITY_MASK 0x3F
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/* DLB*/
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#define REG_STATIC_DRAM_DLB_CONTROL 0x1700
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#define DLB_BUS_OPTIMIZATION_WEIGHTS_REG 0x1704
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#define DLB_AGING_REGISTER 0x1708
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#define DLB_EVICTION_CONTROL_REG 0x170c
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#define DLB_EVICTION_TIMERS_REGISTER_REG 0x1710
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#define DLB_ENABLE 0x1
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#define DLB_WRITE_COALESING (0x1 << 2)
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#define DLB_AXI_PREFETCH_EN (0x1 << 3)
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#define DLB_MBUS_PREFETCH_EN (0x1 << 4)
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#define PREFETCH_NLNSZTR (0x1 << 6)
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/* CPU */
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#define REG_BOOTROM_ROUTINE_ADDR 0x182D0
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#define REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS 12
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#define REG_DRAM_INIT_CTRL_STATUS_ADDR 0x18488
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#define REG_DRAM_INIT_CTRL_TRN_CLK_OFFS 16
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#define REG_CPU_DIV_CLK_CTRL_0_NEW_RATIO 0x000200FF
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#define REG_DRAM_INIT_CTRL_STATUS_2_ADDR 0x1488
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#define REG_CPU_DIV_CLK_CTRL_0_ADDR 0x18700
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#define REG_CPU_DIV_CLK_CTRL_1_ADDR 0x18704
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#define REG_CPU_DIV_CLK_CTRL_2_ADDR 0x18708
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#define REG_CPU_DIV_CLK_CTRL_3_ADDR 0x1870C
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#define REG_CPU_DIV_CLK_CTRL_3_FREQ_MASK 0xFFFFC0FF
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#define REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS 8
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#define REG_CPU_DIV_CLK_CTRL_4_ADDR 0x18710
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#define REG_CPU_DIV_CLK_STATUS_0_ADDR 0x18718
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#define REG_CPU_DIV_CLK_ALL_STABLE_OFFS 8
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#define REG_CPU_PLL_CTRL_0_ADDR 0x1871C
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#define REG_CPU_PLL_STATUS_0_ADDR 0x18724
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#define REG_CORE_DIV_CLK_CTRL_ADDR 0x18740
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#define REG_CORE_DIV_CLK_STATUS_ADDR 0x18744
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#define REG_DDRPHY_APLL_CTRL_ADDR 0x18780
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#define REG_DDRPHY_APLL_CTRL_2_ADDR 0x18784
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#define REG_SFABRIC_CLK_CTRL_ADDR 0x20858
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#define REG_SFABRIC_CLK_CTRL_SMPL_OFFS 8
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/* DRAM Windows */
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#define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
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#define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
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#define REG_XBAR_WIN_4_BASE_ADDR 0x20044
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#define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
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#define REG_FASTPATH_WIN_0_CTRL_ADDR 0x20184
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#define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
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/* SRAM */
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#define REG_CDI_CONFIG_ADDR 0x20220
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#define REG_SRAM_WINDOW_0_ADDR 0x20240
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#define REG_SRAM_WINDOW_0_ENA_OFFS 0
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#define REG_SRAM_WINDOW_1_ADDR 0x20244
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#define REG_SRAM_L2_ENA_ADDR 0x8500
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#define REG_SRAM_CLEAN_BY_WAY_ADDR 0x87BC
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/* PMU */
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#define REG_PMU_I_F_CTRL_ADDR 0x1C090
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#define REG_PMU_DUNIT_BLK_OFFS 16
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#define REG_PMU_DUNIT_RFRS_OFFS 20
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#define REG_PMU_DUNIT_ACK_OFFS 24
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/* MBUS*/
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#define MBUS_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x420)
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#define FABRIC_UNITS_PRIORITY_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x424)
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#define MBUS_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x428)
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#define FABRIC_UNITS_PREFETCH_CONTROL_REG (MV_MBUS_REGS_OFFSET + 0x42c)
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#define REG_PM_STAT_MASK_ADDR 0x2210C
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#define REG_PM_STAT_MASK_CPU0_IDLE_MASK_OFFS 16
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#define REG_PM_EVENT_STAT_MASK_ADDR 0x22120
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#define REG_PM_EVENT_STAT_MASK_DFS_DONE_OFFS 17
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#define REG_PM_CTRL_CONFIG_ADDR 0x22104
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#define REG_PM_CTRL_CONFIG_DFS_REQ_OFFS 18
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#define REG_FABRIC_LOCAL_IRQ_MASK_ADDR 0x218C4
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#define REG_FABRIC_LOCAL_IRQ_PMU_MASK_OFFS 18
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/* Controller revision info */
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#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
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#define PCCRIR_REVID_OFFS 0 /* Revision ID */
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#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS)
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/* Power Management Clock Gating Control Register */
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#define MV_PEX_IF_REGS_OFFSET(if) \
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(if < 8 ? (0x40000 + ((if) / 4) * 0x40000 + ((if) % 4) * 0x4000) \
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: (0x42000 + ((if) % 8) * 0x40000))
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#define MV_PEX_IF_REGS_BASE(unit) (MV_PEX_IF_REGS_OFFSET(unit))
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#define POWER_MNG_CTRL_REG 0x18220
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#define PEX_DEVICE_AND_VENDOR_ID 0x000
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#define PEX_CFG_DIRECT_ACCESS(if, reg) (MV_PEX_IF_REGS_BASE(if) + (reg))
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#define PMC_PEXSTOPCLOCK_OFFS(port) ((port) < 8 ? (5 + (port)) : (18 + (port)))
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#define PMC_PEXSTOPCLOCK_MASK(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port))
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#define PMC_PEXSTOPCLOCK_EN(port) (1 << PMC_PEXSTOPCLOCK_OFFS(port))
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#define PMC_PEXSTOPCLOCK_STOP(port) (0 << PMC_PEXSTOPCLOCK_OFFS(port))
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/* TWSI */
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#define TWSI_DATA_ADDR_MASK 0x7
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#define TWSI_DATA_ADDR_OFFS 1
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/* General */
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#define MAX_CS 4
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/* Frequencies */
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#define FAB_OPT 21
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#define CLK_CPU 12
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#define CLK_VCO (2 * CLK_CPU)
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#define CLK_DDR 12
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/* Cpu Frequencies: */
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#define CLK_CPU_1000 0
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#define CLK_CPU_1066 1
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#define CLK_CPU_1200 2
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#define CLK_CPU_1333 3
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#define CLK_CPU_1500 4
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#define CLK_CPU_1666 5
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#define CLK_CPU_1800 6
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#define CLK_CPU_2000 7
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#define CLK_CPU_600 8
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#define CLK_CPU_667 9
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#define CLK_CPU_800 0xa
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/* Extra Cpu Frequencies: */
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#define CLK_CPU_1600 11
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#define CLK_CPU_2133 12
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#define CLK_CPU_2200 13
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#define CLK_CPU_2400 14
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/* DDR3 Frequencies: */
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#define DDR_100 0
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#define DDR_300 1
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#define DDR_333 1
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#define DDR_360 2
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#define DDR_400 3
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#define DDR_444 4
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#define DDR_500 5
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#define DDR_533 6
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#define DDR_600 7
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#define DDR_640 8
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#define DDR_666 8
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#define DDR_720 9
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#define DDR_750 9
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#define DDR_800 10
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#define DDR_833 11
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#define DDR_HCLK 20
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#define DDR_S 12
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#define DDR_S_1TO1 13
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#define MARGIN_FREQ DDR_400
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#define DFS_MARGIN DDR_100
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|
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#define ODT_OPT 16
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#define ODT20 0x200
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#define ODT30 0x204
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#define ODT40 0x44
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#define ODT120 0x40
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#define ODT120D 0x400
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|
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#define MRS_DELAY 100
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|
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#define SDRAM_WL_SW_OFFS 0x100
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|
#define SDRAM_RL_OFFS 0x0
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#define SDRAM_PBS_I_OFFS 0x140
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#define SDRAM_PBS_II_OFFS 0x180
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#define SDRAM_PBS_NEXT_OFFS (SDRAM_PBS_II_OFFS - SDRAM_PBS_I_OFFS)
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#define SDRAM_PBS_TX_OFFS 0x180
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#define SDRAM_PBS_TX_DM_OFFS 576
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#define SDRAM_DQS_RX_OFFS 1024
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#define SDRAM_DQS_TX_OFFS 2048
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#define SDRAM_DQS_RX_SPECIAL_OFFS 5120
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#define LEN_STD_PATTERN 16
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|
#define LEN_KILLER_PATTERN 128
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#define LEN_SPECIAL_PATTERN 128
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#define LEN_PBS_PATTERN 16
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#endif /* __DDR3_AXP_H */
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