317 lines
8.0 KiB
C
317 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/**
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* ti_usb_phy.c - USB3 and USB3 PHY programming for dwc3
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*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
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*
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* Taken from Linux Kernel v3.16 (drivers/phy/phy-ti-pipe3.c and
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* drivers/phy/phy-omap-usb2.c) and ported to uboot.
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*
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* "commit 56042e : phy: ti-pipe3: Fix suspend/resume and module reload" for
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* phy-ti-pipe3.c
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*
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* "commit eb82a3 : phy: omap-usb2: Balance pm_runtime_enable() on probe failure
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* and remove" for phy-omap-usb2.c
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*/
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#include <common.h>
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#include <malloc.h>
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#include <ti-usb-phy-uboot.h>
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#include <usb/lin_gadget_compat.h>
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#include <linux/ioport.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <dm.h>
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#include "linux-compat.h"
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#define PLL_STATUS 0x00000004
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#define PLL_GO 0x00000008
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#define PLL_CONFIGURATION1 0x0000000C
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#define PLL_CONFIGURATION2 0x00000010
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#define PLL_CONFIGURATION3 0x00000014
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#define PLL_CONFIGURATION4 0x00000020
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#define PLL_REGM_MASK 0x001FFE00
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#define PLL_REGM_SHIFT 0x9
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#define PLL_REGM_F_MASK 0x0003FFFF
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#define PLL_REGM_F_SHIFT 0x0
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#define PLL_REGN_MASK 0x000001FE
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#define PLL_REGN_SHIFT 0x1
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#define PLL_SELFREQDCO_MASK 0x0000000E
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#define PLL_SELFREQDCO_SHIFT 0x1
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#define PLL_SD_MASK 0x0003FC00
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#define PLL_SD_SHIFT 10
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#define SET_PLL_GO 0x1
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#define PLL_LDOPWDN BIT(15)
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#define PLL_TICOPWDN BIT(16)
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#define PLL_LOCK 0x2
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#define PLL_IDLE 0x1
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#define OMAP_CTRL_DEV_PHY_PD BIT(0)
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#define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
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#define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
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#define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
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#define OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
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#define OMAP_CTRL_USB3_PHY_TX_RX_POWERON 0x3
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#define OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF 0x0
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#define OMAP_CTRL_USB2_PHY_PD BIT(28)
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#define AM437X_CTRL_USB2_PHY_PD BIT(0)
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#define AM437X_CTRL_USB2_OTG_PD BIT(1)
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#define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
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#define AM437X_CTRL_USB2_OTGSESSEND_EN BIT(20)
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static LIST_HEAD(ti_usb_phy_list);
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typedef unsigned int u32;
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struct usb3_dpll_params {
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u16 m;
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u8 n;
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u8 freq:3;
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u8 sd;
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u32 mf;
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};
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struct usb3_dpll_map {
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unsigned long rate;
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struct usb3_dpll_params params;
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struct usb3_dpll_map *dpll_map;
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};
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struct ti_usb_phy {
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void __iomem *pll_ctrl_base;
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void __iomem *usb2_phy_power;
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void __iomem *usb3_phy_power;
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struct usb3_dpll_map *dpll_map;
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struct list_head list;
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int index;
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};
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static struct usb3_dpll_map dpll_map_usb[] = {
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{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
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{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
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{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
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{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
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{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
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{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
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{ }, /* Terminator */
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};
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static inline unsigned int ti_usb3_readl(void __iomem *base, u32 offset)
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{
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return readl(base + offset);
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}
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static inline void ti_usb3_writel(void __iomem *base, u32 offset, u32 value)
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{
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writel(value, base + offset);
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}
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#ifndef CONFIG_AM43XX
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static struct usb3_dpll_params *ti_usb3_get_dpll_params(struct ti_usb_phy *phy)
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{
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unsigned long rate;
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struct usb3_dpll_map *dpll_map = phy->dpll_map;
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rate = get_sys_clk_freq();
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for (; dpll_map->rate; dpll_map++) {
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if (rate == dpll_map->rate)
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return &dpll_map->params;
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}
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dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
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return NULL;
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}
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static int ti_usb3_dpll_wait_lock(struct ti_usb_phy *phy)
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{
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u32 val;
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do {
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val = ti_usb3_readl(phy->pll_ctrl_base, PLL_STATUS);
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if (val & PLL_LOCK)
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break;
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} while (1);
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return 0;
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}
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static int ti_usb3_dpll_program(struct ti_usb_phy *phy)
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{
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u32 val;
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struct usb3_dpll_params *dpll_params;
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if (!phy->pll_ctrl_base)
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return -EINVAL;
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dpll_params = ti_usb3_get_dpll_params(phy);
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if (!dpll_params)
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return -EINVAL;
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val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGN_MASK;
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val |= dpll_params->n << PLL_REGN_SHIFT;
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ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
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val &= ~PLL_SELFREQDCO_MASK;
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val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
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ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
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val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
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val &= ~PLL_REGM_MASK;
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val |= dpll_params->m << PLL_REGM_SHIFT;
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ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
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val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
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val &= ~PLL_REGM_F_MASK;
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val |= dpll_params->mf << PLL_REGM_F_SHIFT;
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ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
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val = ti_usb3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
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val &= ~PLL_SD_MASK;
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val |= dpll_params->sd << PLL_SD_SHIFT;
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ti_usb3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
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ti_usb3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
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return ti_usb3_dpll_wait_lock(phy);
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}
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#endif
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void ti_usb2_phy_power(struct ti_usb_phy *phy, int on)
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{
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u32 val;
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val = readl(phy->usb2_phy_power);
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if (on) {
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#if defined(CONFIG_DRA7XX)
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if (phy->index == 1)
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val &= ~OMAP_CTRL_USB2_PHY_PD;
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else
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val &= ~OMAP_CTRL_DEV_PHY_PD;
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#elif defined(CONFIG_AM43XX)
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val &= ~(AM437X_CTRL_USB2_PHY_PD |
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AM437X_CTRL_USB2_OTG_PD);
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val |= (AM437X_CTRL_USB2_OTGVDET_EN |
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AM437X_CTRL_USB2_OTGSESSEND_EN);
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#endif
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} else {
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#if defined(CONFIG_DRA7XX)
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if (phy->index == 1)
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val |= OMAP_CTRL_USB2_PHY_PD;
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else
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val |= OMAP_CTRL_DEV_PHY_PD;
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#elif defined(CONFIG_AM43XX)
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val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
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AM437X_CTRL_USB2_OTGSESSEND_EN);
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val |= (AM437X_CTRL_USB2_PHY_PD |
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AM437X_CTRL_USB2_OTG_PD);
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#endif
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}
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writel(val, phy->usb2_phy_power);
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}
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#ifndef CONFIG_AM43XX
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void ti_usb3_phy_power(struct ti_usb_phy *phy, int on)
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{
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u32 val;
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u32 rate;
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rate = get_sys_clk_freq();
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rate = rate/1000000;
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if (!phy->usb3_phy_power)
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return;
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val = readl(phy->usb3_phy_power);
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if (on) {
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val &= ~(OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK |
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OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_MASK);
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val |= (OMAP_CTRL_USB3_PHY_TX_RX_POWERON) <<
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OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
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val |= rate <<
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OMAP_CTRL_USB3_PHY_PWRCTL_CLK_FREQ_SHIFT;
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} else {
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val &= ~OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_MASK;
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val |= OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF <<
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OMAP_CTRL_USB3_PHY_PWRCTL_CLK_CMD_SHIFT;
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}
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writel(val, phy->usb3_phy_power);
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}
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#endif
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/**
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* ti_usb_phy_uboot_init - usb phy uboot initialization code
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* @dev: struct ti_usb_phy_device containing initialization data
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*
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* Entry point for ti usb phy driver. This driver handles initialization
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* of both usb2 phy and usb3 phy. Pointer to ti_usb_phy_device should be
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* passed containing base address and other initialization data.
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* Returns '0' on success and a negative value on failure.
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*
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* Generally called from board_usb_init() implemented in board file.
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*/
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int ti_usb_phy_uboot_init(struct ti_usb_phy_device *dev)
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{
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struct ti_usb_phy *phy;
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phy = devm_kzalloc(NULL, sizeof(*phy), GFP_KERNEL);
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if (!phy) {
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dev_err(NULL, "unable to alloc mem for TI USB3 PHY\n");
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return -ENOMEM;
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}
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phy->dpll_map = dpll_map_usb;
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phy->index = dev->index;
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phy->pll_ctrl_base = dev->pll_ctrl_base;
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phy->usb2_phy_power = dev->usb2_phy_power;
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phy->usb3_phy_power = dev->usb3_phy_power;
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#ifndef CONFIG_AM43XX
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ti_usb3_dpll_program(phy);
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ti_usb3_phy_power(phy, 1);
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#endif
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ti_usb2_phy_power(phy, 1);
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mdelay(150);
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list_add_tail(&phy->list, &ti_usb_phy_list);
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return 0;
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}
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/**
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* ti_usb_phy_uboot_exit - usb phy uboot cleanup code
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* @index: index of this controller
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*
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* Performs cleanup of memory allocated in ti_usb_phy_uboot_init.
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* index of _this_ controller should be passed and should match with
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* the index passed in ti_usb_phy_device during init.
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*
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* Generally called from board file.
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*/
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void ti_usb_phy_uboot_exit(int index)
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{
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struct ti_usb_phy *phy = NULL;
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list_for_each_entry(phy, &ti_usb_phy_list, list) {
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if (phy->index != index)
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continue;
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ti_usb2_phy_power(phy, 0);
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#ifndef CONFIG_AM43XX
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ti_usb3_phy_power(phy, 0);
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#endif
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list_del(&phy->list);
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kfree(phy);
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break;
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}
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}
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